Versatile RAM for a programmable logic device

A programmable logic device having a versatile Random Access Memory (RAM), the device comprising:

• a plurality of logic array blocks, each of the logic array blocks comprising a plurality of logic elements and an embedded RAM memory block that is addressable by the plurality of logic elements;
• a plurality of multiplexers adapted to drive output signals from the plurality of logic array blocks onto a selected portion of a plurality of global signal lines;
• an embedded array block logic array block (EAB LAB), wherein the EAB LAB is adapted to receive a plurality of signals from a general interconnect, register at least a portion of the plurality of signals and drive at least a portion of the plurality of signals via the global signal lines to one of the plurality of RAM memory blocks and the plurality of logic array blocks, the global signal lines adapted to:
• in a first configuration of the programmable logic device, provide address signals that, at least in part, specify a location in at least one RAM memory block, the location that is adapted to be either written to or read from;
• and
• in a second configuration of the programmable logic device, provide a plurality of input signals to a plurality of inputs of at least one logic element;
• and
• an embedded array block output logic array block (EAB Output LAB), wherein the EAB Output LAB is adapted to receive a plurality of signals from global signal lines, register at least a portion of the plurality of signals and drive at least a portion of the plurality of signals onto a general interconnect.

A method of addressing Random Access Memory (RAM) in a programmable logic device, the programmable logic device including a plurality of logic array blocks having a plurality of logic elements and an embedded RAM memory block that is addressable by the plurality of logic elements, the method comprising:

• in a first configuration of the programmable logic device, providing address signals from an embedded array block logic array block (EAB LAB) to at least one RAM memory block associated with a logic array block;
• in a second configuration of the programmable logic device, providing input signals from the EAB LAB to at least one logic element of the logic array block;
• and
• combining the plurality of logic elements to act as a single logic element by, at least in part, utilizing the outputs of the plurality of RAM memory blocks as data inputs to the plurality of logic elements.