Method and apparatus to reduce latency and improve throughput of input/output data in a processor
AssigneeIntel Corporation
InventorsD. Michael Bell, Anil Vasudevan
Life of this patent
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Abstract
Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.
Claims20
A method comprising:
- receiving a first portion and a second portion of at least one packet at an input/output device;
- and
- transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor;
- and
- transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device.
An apparatus comprising:
- a register circuit to receive a first portion of a packet from an input/output device;
- a cache memory circuit to receive a second portion of the packet;
- and
- a processing unit to process the first and second portions of the packet based on instructions in the processing unit, the processing unit and the register circuit residing on a processor, wherein the first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor, and wherein the second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.
An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:
- receiving a first portion and a second portion of at least one packet at an input/output device;
- and
- transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor;
- and
- transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device.
Dependencies are inferred from the claim text.