Segregated caching of linked lists for USB
AssigneeNVIDIA Corporation
InventorJohn Berendsen
Life of this patent
Estimating the term…
Abstract
Circuits, methods, and apparatus that increase utilization of available USB bandwidth, limit the amount of data accessed from memory, and provide for parallel requests for data from memory. An exemplary embodiment of the present invention caches a pointer for each transfer descriptor in a periodic and async schedule. Several transfer descriptors are also cached. Caching pointers reduces the time needed to organize the needed transfer descriptors to be transmitted. Caching several transfer descriptors eliminates the need to access the main memory each time they are needed. Also, if more transfer descriptors are needed beyond those in cache, memory requests for multiple transfer descriptors may be done in parallel since their pointers are available in cache.
Claims19
A computing system comprising:
- a CPU;
- a Northbridge coupled to the CPU;
- a Southbridge coupled to the Northbridge;
- and
- a system memory coupled to the Northbridge;
- wherein the Southbridge comprises:
- a PC interface configured to couple the Southbridge to the Northbridge;
- and
- a USB controller coupled to the PC interface, wherein the USB controller comprises:
- a scheduler that processes at least one schedule of transfer descriptors;
- a pointer cache coupled to the scheduler and configured to cache a plurality of pointers identifying locations in the system memory for the transfer descriptors in the schedule, wherein the pointer cache stores the pointer for each of the transfer descriptors in the schedule;
- and
- a data cache coupled to the scheduler and configured to cache only a portion of the plurality of transfer descriptors in the schedule.
A USB controller comprising:
- a scheduler;
- a pointer cache coupled to the scheduler and configured to cache a plurality of pointers identifying memory locations for a plurality of transfer descriptors;
- and
- a data cache coupled to the scheduler and configured to cache at least two of the plurality of transfer descriptors,
- wherein each entry in the pointer cache comprises one or more bits indicating whether activity is required by the corresponding transfer descriptor.
A method of transferring data over a Universal Serial Bus comprising:
- in a first microframe, traversing a periodic schedule, the periodic schedule comprising a plurality of transfer descriptors;
- determining which transfer descriptors require work to be done;
- storing a pointer and a flag for each transfer descriptor in a first portion of a first cache, the pointer corresponding to a memory location for the transfer descriptor and the flag indicating whether the transfer descriptor requires work to be done;
- and
- storing a plurality of transfer descriptors in a second cache.
A method of transferring data over a Universal Serial Bus comprising:
- determining a plurality of transfer descriptors, each transfer descriptor stored in a memory location;
- caching a plurality of pointers, each pointer identifying the memory location of a transfer descriptor;
- and
- caching a first number of the plurality of transfer descriptors, where the first number is greater than one and less than the number of pointers cached.
Dependencies are inferred from the claim text.