Method and apparatus using attached hardware subsystem to communicate between attached hosts

#These teachings relate generally to digital data processors and message passing techniques and, more specifically, relate to interrupt-driven inter-processor communication techniques.

#In a multiple processor environment it is typically the case that some mechanism exists for providing inter-processor communication (IPC). Reference in this regard can be had, as an example, to U.S. Pat. No.: 5,459,836, “Inter-Processor Communication Net”, by Bruce E. Whittaker et al. In this approach each processor in a network of processors is provided with a hardware IPC unit that connects via an IPC signal network to the IPC hardware units of each of the other processors. Each IPC hardware unit provides equal access to the IPC signal network, and also permits multiple signal messages to be received and buffered until serviced by the software of the receiving processor. The software of the receiving processor is made aware of the arrival of a message through an interrupt that is generated by the receiving processor's IPC hardware unit.

#Other message passing techniques, in particular interrupt-driven message passing techniques, can be found in commonly-assigned U.S. Pat. No.: 6,105,071, as well as in U.S. Pat. Nos.: 4,633,392, 5,999,969 and 6,321,289.

#The foregoing and other aspects of these teachings are made more evident in the following Detailed Description of the Preferred Embodiments, when read in conjunction with the attached Drawing Figures, wherein:

#FIG. 1 is a simplified high level block diagram of a data processing system that is suitable for practicing the teachings of this invention;

#FIG. 2 shows an example of the format of the Send Message command;

#Reference is made to FIG. 1 for showing a data processing system 10, which may also be referred to as a storage area network. The system 10 includes, in the illustrated embodiment, a hardware subsystem that can be embodied as a Disk Control Unit (DCU) 12. The DCU 12 is assumed to be bidirectionally connected to a Mass Storage Unit (MSU) 14. The MSU 14 may be a single large disk, although in practice it will contain a plurality of disk drives arranged in ranks or arrays. The ranks of disks can be configured in a RAID configuration, e.g., a RAID 5 configuration, or as non-RAID arrays. While shown in FIG. 1 as a simple bidirectional connection 13, in actuality the interface between the DCU 12 and the MSU 14 can be made through a plurality of device adapters (DAs) in a manner known in the art.

#Connected to the DCU 12 are a plurality of host processors 16, four of which are shown for convenience and designated HOST_1, HOST_2, HOST_3 and HOST_4. More or less than four hosts 16 can be used, and in one exemplary embodiment there may be up to 16 hosts connected to the DCU 12. The hosts 16 may be the same type of data processor, or each may be a different type of data processor from the same manufacturer, or each may be a different type of data processor from different manufacturers. As an example, the hosts 16 can include data processors and servers available from the assignee of this patent application such as, but not limited to: a System/390® computer server system running OS/390®, a Reduced Instruction Set Computer (RISC) system such as one known as the RS/600™ system, and an xSeries™ system such as the NetFinity® system, Registered Trademarks and Trademarks of the International Business Machines Corporation. Data processors and servers manufactured by others can also be used and connected as hosts to the DCU 12.

#The hosts 16 are connected to the DCU 12 through channels 18, designated for convenience as CHANNEL_1, CHANNEL_2, CHANNEL_3 and CHANNEL_4. Each channel 18 is terminated at the DCU 12 with a Host Adapter (HA) 19, which can take the form of, for example, a SCSI input/output (I/O) interface or an Enterprise Systems Connection (ESCON®) fiber I/O interface, a Registered Trademark of the International Business Machines Corporation.