Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations

A finite impulse response (FIR) filter circuit for filtering input data samples, comprising:

• a plurality of computational unit circuits arranged in a systolic array having a plurality of columns and a plurality of rows, each column of computational unit circuits corresponding to one of a tap and a phase and each row of computational unit circuits corresponding to the other of a tap and a phase, each tap and each phase of the systolic array being adapted to receive concurrently an input data sample from a demultiplexer during each array clock cycle, each computational unit circuit in a tap other than a last tap comprising:
• a first input signal line for receiving an input data sample,
• a second input signal line for receiving a coefficient,
• a third input signal line for receiving a supplied value,
• circuitry for computing a value based on the received input data sample, the coefficient, and the supplied value,
• a first output signal line for communicating the value computed by that computational unit circuit to a computational unit circuit in a neighboring tap, and
• a second output signal line for communicating the received input data sample to a computational unit circuit in a neighboring phase of the neighboring tap.

A signal processor circuit, comprising:

• a demultiplexer circuit receiving input data samples;
• and
• a first finite impulse response (FIR) filter circuit in communication with the demultiplexer circuit for obtaining the input data samples therefrom, the first FIR filter circuit including a first plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases and a first set of coefficients used by the first plurality of computational unit circuits to compute values based on the input data samples;
• and
• a second FIR filter circuit in communication with the demultiplexor circuit for obtaining the input data samples therefrom, the second FIR filter circuit including a second plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases and a second set of coefficients different from the first set of coefficients, the second set of coefficients being used by the second plurality of computational unit circuits to compute values based on the input data samples,
• wherein at least one of the computational unit circuits in a last phase of the second FIR filter circuit is in communication with one of the computational unit circuits in a first phase of the first FIR filter circuit for communicating an input data sample thereto during each array clock cycle, and wherein during each array clock cycle the demultiplexer circuit forwards input data samples concurrently to each tap and to each phase of computational unit circuits.

A method of linearly filtering input data samples, compnsing:

• receiving at a demultiplexer circuit input data samples at an input data rate;
• forwarding by the demultiplexer circuit the input data samples concurrently to a first tap and a first phase of an array of computational unit circuits of a finite impulse filter (FIR) circuit having a plurality of taps and a plurality of phases;
• and
• receiving by the computational unit circuits the input data samples forwarded by the demultiplexer circuit and computing values based on these received input data samples at an array clock rate that is slower than the input data rate.