Software state replay

A computer readable storage medium having computer-executable instructions which when executed on a computing device perform a method of analyzing a partition of a circuit design, comprising:

• determining a predetermined partition of a circuit design being emulated;
• sampling an emulator to obtain one or more input values provided at a first time to the predetermined partition of the circuit design being emulated;
• sampling the emulator to obtain one or more first state values produced by the circuit design partition at the first time;
• using the obtained one or more input values and the one or more first state values to execute a software model that describes the operation of the circuit design partition, so as to calculate one or more second state values produced by the circuit design partition at a second time;
• and
• registering the one or more second state values in a tangible medium.

A method of analyzing a circuit design partition, comprising:

• determining a predetermined first partition of a circuit design;
• sampling an emulator emulating the predetermined partition of the circuit design to obtain:
• each cycle of a first clock signal being provided to the emulated circuit design partition during a defined analysis period,
• each input value provided to the emulated circuit design partition at every cycle during the defined analysis period, and
• one or more first state values produced by the emulated circuit design partition at specified state value sample times over the defined analysis period;
• using the obtained input values, the first clock signals and one or more sampled state values to execute a first software model that describes the operation of the circuit design partition, so as to calculate state values produced by the circuit design partition during intervals between the specified state value sample times over the defined analysis period;
• and
• registering at least the calculated state values in a tangible medium.

A computer readable storage medium having computer-executable instructions that, when executed on a computing device, perform a method of analyzing a circuit design partition comprising:

• determining a predetermined partition of a circuit design;
• sampling an emulator emulating the predetermined partition of the circuit design to obtain:
• each cycle of a clock signal being provided to the emulated circuit design partition during a defined analysis period;
• each input value provided to the emulated circuit design partition at every cycle during the defined analysis period;
• and
• one or more state values produced by the emulated circuit design partition at specified state value sample times over the defined analysis period;
• using the obtained input values, clock signals and one or more sampled state values to execute a software model that describes the operation of the circuit design partition, so as to calculate state values produced by the circuit design partition during intervals between the specified state value sample times over the defined analysis period;
• and
• registering at least the calculated state values in a tangible medium.