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US 7,480,609 B1Granted
Applying distributed simulation techniques to hardware emulation
AssigneeSun Microsystems, Inc.
InventorsCarl Cavanagh, Steven A. Sivier
Life of this patent
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Abstract
A system for applying distributed software simulation techniques to hardware emulation may include a first hardware emulator mounted on a first expansion board at a first host, and a second hardware emulator mounted on a second expansion board at a second host. The first hardware emulator may be configured to emulate a first portion of a system under test, and the second hardware emulator may be configured to emulate a second portion of the system under test, and the first and second hardware emulators may coordinate an emulation of the system under test using one or more messages, i.e., a coordination of an emulation of the system under test may be accomplished using communications between the first and second hardware emulators.
Claims19
A system comprising:
- a first computer host including a first hardware emulator mounted on a first expansion board;
- a second computer host including a second hardware emulator mounted on a second expansion board;
- and
- an emulation controller coupled to control the first hardware emulator and the second hardware emulator;
- wherein the first hardware emulator is configured to emulate a first portion of a system under test, and the second hardware emulator is configured to emulate a second portion of the system under test, and wherein the first and second hardware emulators are configured to coordinate an emulation of the system under test using one or more messages;
- wherein the first hardware emulator includes a first field programmable gate array (FPGA) device;
- wherein the second hardware emulator includes a second field programmable gate array (FPGA) device;
- and
- wherein the emulation controller is configured to:
- distribute the first portion of the system under test to the first hardware emulator by issuing commands that cause the first FPGA device to be programmed to emulate the first portion under test;
- distribute the second portion of the system under test to the second hardware emulator by issuing additional commands that cause the second FPGA device to emulate the second portion under test;
- and
- monitor a state of the first and second hardware emulators during the emulation of the system under test;
- wherein the first and second hardware emulators are further configured to emulate the first and second portions, respectively, of the system under test in a series of emulation timesteps, wherein each emulation timestep includes a zero time phase emulation and real time phase emulation, wherein during the zero time phase emulation, a state of an emulation of the respective portion of the system under test is frozen while input signals of the emulation of the respective portion are changed and output signals of the emulation of the respective portion are sampled, and wherein during the real time phase emulation, the state of the emulation of the respective portion of the system under test is iteratively changed in response to sampling output signals of the emulation of the respective portion and driving input signals of the emulation of the respective portion, and wherein the first and second hardware emulators are each configured to generate a corresponding completion message in response to completing the zero time phase emulation;
- wherein the emulation controller is configured to cause the first and second hardware emulators to each initiate the real time phase emulation in response to receiving the completion messages from both the first hardware emulator and the second hardware emulator.
12 more elements
A system comprising:
- a first computer host including a first hardware emulator mounted on a first expansion board;
- a second computer host including a second hardware emulator mounted on a second expansion board;
- and
- an emulation controller coupled to control the first hardware emulator and the second hardware emulator;
- a hub;
- wherein the first hardware emulator is configured to emulate a first portion of a system under test, and the second hardware emulator is configured to emulate a second portion of the system under test, and wherein the first and second hardware emulators are configured to coordinate an emulation of the system under test by transmitting one or more messages between one another through the hub;
- wherein the first hardware emulator includes a first field programmable gate array (FPGA) device and a first programmable logic device (PLD) operable to program the first FPGA device;
- wherein the second hardware emulator includes a second field programmable gate array (FPGA) device and a second programmable logic device (PLD) operable to program the second FPGA device;
- wherein the emulation controller is configured to:
- issue commands that cause the first PLD device to program the first FPGA device to emulate the first portion under test;
- issue additional commands that cause the second PLD device to program the second FPGA device to emulate the second portion under test;
- and
- monitor a state of the first and second hardware emulators during the emulation of the system under test;
- and
- wherein the first and second hardware emulators are further configured to emulate the first and second portions, respectively, of the system under test in a series of emulation timesteps, wherein each emulation timestep includes a zero time phase emulation and real time phase emulation, wherein during the zero time phase emulation, a state of an emulation of the respective portion of the system under test is frozen while input signals of the emulation of the respective portion are changed and output signals of the emulation of the respective portion are sampled, and wherein during the real time phase emulation, the state of the emulation of the respective portion of the system under test is iteratively changed in response to sampling output signals of the emulation of the respective portion and driving input signals of the emulation of the respective portion, and wherein the first and second hardware emulators are each configured to generate a corresponding completion message in response to completing the zero time phase emulation;
- wherein the emulation controller is configured to cause the first and second hardware emulators to each initiate the real time phase emulation in response to receiving the completion messages from both the first hardware emulator and the second hardware emulator.
13 more elements
Dependencies are inferred from the claim text.