Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty

A computer implemented method for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit, the simulated semiconductor circuit defined at least in part by a plurality of input parameters, the method comprising:

• determining, from a distribution of first values of a given input parameter, a plurality of the first values to use when calculating a corresponding plurality of second values for each of one or more output parameters;
• calculating, by using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the coffesponding plurality of second values for each of the one or more output parameters, wherein the one or more output parameters correspond to the one or more given interconnects wherein each of the second values corresponds to at least one of the determined plurality of first values, wherein the plurality of input parameters comprises a metal layer thickness and a via layer thickness, wherein the metal layer thickness and the via layer thickness are correlated, correlation of which is defined at least in part by a correlation coefficient accounting for how modification of one affects the other, and wherein calculating is performed using the correlation coefficient for the correlated metal layer thickness and via layer thickness;
• and
• presenting on at least one display the plurality of second values to a user.