Wireless device having a distinct hardware accelerator to support data compression protocols dedicated to GSM (V.42)

A wireless terminal that comprises:

• a Radio Frequency (RF) front end;
• a baseband processor communicatively coupled to the RF front end that receives incoming information to be compressed or decompressed according to a data compression protocol;
• a shared memory coupled to the baseband processor to store the information;
• and
• a data compression/decompression accelerator module operably coupled to the baseband processor and the shared memory to perform compression or decompression operation on the stored information according to the data compression protocol, wherein the data compression/decompression accelerator module includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module, in which the baseband processor generates an instruction to the data compression/decompression accelerator module, wherein the instruction includes a pointer to be passed to the data compression/decompression accelerator module to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target for the performed process, wherein upon completion of the compression or decompression operation, the data compression/decompression accelerator module returns compressed or decompressed information back to the shared memory for retrieval by the baseband processor.

A method to process information within a wireless terminal comprising:

• receiving information at a processing engine;
• determining if a compression or decompression operation is needed in the processing engine;
• storing the information in a shared memory if compression or decompression operation is needed for retrieval of the information by a data compression/decompression accelerator module;
• generating an instruction to the data compression/decompression accelerator module from the processing engine, in which the instruction includes a pointer to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target to perform the process;
• performing the compression or decompression operation in the data compression/decompression accelerator module that includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module;
• storing the compressed or decompressed information in the shared memory;
• and
• retrieving the stored compressed or decompressed information by the processing engine.