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US 7,480,361 B1Granted
Phase lock detector
AssigneeXilinx, Inc.
InventorsQi Zhang, Atul Ghia
Life of this patent
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Abstract
Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.
Claims19
A phase lock detection circuit, comprising:
- a synchronization circuit coupled to receive a reference signal and configured to provide a derivative signal;
- the derivative signal being derived from the reference signal;
- a phase lock detector coupled to receive the reference signal and the derivative signal;
- the phase lock detector configured to provide a cycle lock signal;
- the cycle lock signal indicating whether a phase lock exists as between the reference signal and the derivative signal within a lock window for a clock cycle;
- and
- an asymmetrical low pass filter coupled to receive the cycle lock signal;
- wherein the asymmetrical low pass filter is configured to unequally weight a lock condition relative to an out-of-lock condition indicated, the lock condition and the out-of-lock condition indicated by the cycle lock signal.
5 more elements
A phase lock detector, comprising:
- a first delay coupled to receive a reference signal and configured to provide a delayed version of the reference signal;
- a second delay coupled to receive a feedback signal and configured to provide a delayed version of the feedback signal, the feedback signal being a version of the reference signal;
- a first phase detector coupled to receive the feedback signal and the delayed version of the reference signal;
- the first phase detector configured to compare phase of the feedback signal and the delayed version of the reference signal to provide a first phase relation signal;
- a second phase detector coupled to receive the delayed version of the feedback signal and the reference signal;
- the second phase detector configured to compare phase of the delayed version of the feedback signal and the reference signal to provide a second phase relation signal;
- combinational logic coupled to receive the first phase relation signal and the second phase relation signal to provide a lock indicator signal, the lock indicator signal indicating whether the reference signal and the feedback signal are in a lock window;
- a register having a data input coupled to receive the lock indicator signal and a clock input coupled to receive a clocking signal;
- and
- an inverter coupled to receive the reference signal and provide the clocking signal.
7 more elements
A method for providing a lock window, comprising:
- inputting a feedback signal to a first phase detector and to a first delay;
- inputting a reference signal to a second phase detector and to a second delay;
- obtaining an output of the first delay for input to the second phase detector to provide a first portion of the lock window;
- obtaining an output of the second delay for input to the first phase detector to provide a second portion of the lock window;
- combining the first portion and the second portion of the lock window to provide a lock signal indicative of the lock window;
- and
- registering the lock signal with an inverted version of the reference signal.
4 more elements
An integrated circuit comprising:
- a synchronization circuit, the synchronization circuit configured to receive a reference signal and to provide a derivative signal based on the reference signal;
- and
- a phase lock detector, the phase lock detector comprising:
- a first delay coupled to receive the reference signal and configured to provide a delayed version of the reference signal;
- a second delay coupled to receive the derivative signal and configured to provide a delayed version of the derivative signal;
- a first phase detector coupled to receive the derivative signal and the delayed version of the reference signal;
- the first phase detector configured to compare phase of the derivative signal and the delayed version of the reference signal to provide a first phase relation signal;
- a second phase detector coupled to receive the delayed version of the derivative signal and the reference signal;
- the second phase detector configured to compare phase of the delayed version of the derivative signal and the reference signal to provide a second phase relation signal;
- combinational logic coupled to receive the first phase relation signal and the second phase relation signal to provide a lock indicator signal, the lock indicator signal indicating whether the reference signal and the feedback signal are in a lock window;
- and
- asymmetrical low pass filter coupled to receive the lock indicator signal, the asymmetrical low pass filter configured to unequally weight a lock condition relative to an out-of-lock condition.
9 more elements
Dependencies are inferred from the claim text.