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US 7,480,360 B2Granted
Regulating a timing between a strobe signal and a data signal
AssigneeIntel Corporation
InventorsBruce Querbach, Mohammad A. Abdallah, Amjad M. A. Khan, Mir M. Hossain, Sanjib M. Sarkar
Life of this patent
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Abstract
A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.
Claims19
A method comprising:
- in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus;
- based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line, the regulating comprising:
- based on the communication, determining a subset of delays within a range of delays which may be applied to the strobe signal to cause the strobe signal to be synchronized to a data eye of the data bit signal and applying a delay within the range to the strobe signal to generate a delayed strobe signal;
- in response to the training mode, evaluating the boundaries of the range;
- and
- selectively moving the boundaries based on the evaluation.
3 more elements
A system comprising:
- a bus comprising a data bit line and a clock line;
- a dynamic random access memory coupled to the bus;
- a processor coupled to the bus;
- an agent coupled to the bus;
- and
- a circuit to based on a communication between the processor and the agent in a training mode, regulate a timing between a strobe signal and a signal that propagates over the data bit line, the regulation comprising based on the communication, determining a subset of delays within a range of delays and applying a delay within the range to the strobe signal to generate a delayed strobe signal,
- wherein the circuit is adapted to in response to the training mode, evaluate the boundaries of the range and selectively move the boundaries based on the evaluation.
4 more elements
A bus interface comprising:
- delay circuits, each delay circuit to delay a strobe signal to produce a delayed strobe signal associated with a different data bit line of a bus;
- buffer circuits, each buffer circuit being associated with a different one of the delayed strobe signals and buffer circuit to capture data from a different one of the data bit lines in response to the associated delayed strobe signal;
- and
- circuitry coupled to the delay circuits to, based on communication over the bus in a training mode, regulate timing of the delayed strobe signals, the regulation comprising based on the communication, determining a subset of delays within a range of delays and applying a delay within the range to the strobe signal to generate a delayed strobe signal,
- wherein the circuitry in response to the training mode evaluates the boundaries of the range and selectively moves the boundaries based on the evaluation.
2 more elements
An article comprising a computer accessible storage medium storing instructions to, when executed, cause a computer to:
- based on a communication between bus agents in a training mode, regulate a timing between a strobe signal and a signal that propagates over a data bit line of a bus, the regulating comprising based on the communication, determine a subset of delays within a range of delays which may be applied to strobe signal to cause the strobe signal to be synchronized to a data eye of the data bit signal and apply a delay within the range to the strobe signal to generate a delayed strobe signal;
- in response to the training mode, evaluate the boundaries of the range;
- and
- selectively move the boundaries based on the evaluation.
1 more element
Dependencies are inferred from the claim text.