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US 7,480,358 B2Granted
CDR-based clock synthesis
AssigneeInfineon Technologies AG
InventorsHamid Partovi, William P. Evans
Life of this patent
Estimating the term…
Abstract
A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.
Claims28
A clock synthesizer apparatus, comprising:
- a clock and data recovery (CDR) circuit including a serial data input, said CDR circuit operable when a serial data stream is applied thereto via said serial data input for recovering a clock signal from the serial data stream;
- a clock source input for receiving a clock source signal having a fixed transition density, said clock source input coupled to said serial data input for applying said clock source signal to said CDR circuit;
- and
- said CDR circuit responsive to said clock source signal received at said serial data input thereof for producing a desired clock signal.
1 more element
A serial data transceiver apparatus, comprising:
- a receive data input for receiving an input serial data stream;
- a first clock and data recovery (CDR) circuit coupled to said receive data input for deserializing said input serial data stream;
- a data serializer for converting parallel data into an output serial data stream, said data serializer having a clock input for receiving a transmit serialization clock signal, said data serializer for producing said output serial data stream based on said transmit serialization clock signal;
- a clock synthesizer apparatus coupled to said clock input for providing said transmit serialization clock signal, including a second CDR circuit having a serial data input, said second CDR circuit operable when a serial data stream is applied thereto via said serial data input for recovering a clock signal from the serial data stream, said clock synthesizer apparatus including a clock source input for receiving a clock source signal, said clock source input coupled to said serial data input for applying said clock source signal to said second CDR circuit, said second CDR circuit responsive to said clock source signal for producing said transmit serialization clock signal;
- and
- a transmit data output coupled to said data serializer for transmitting said output serial data stream.
3 more elements
A method of synthesizing a clock signal, comprising:
- providing a clock source signal having a fixed transition density;
- providing said clock source signal to a serial data input of a clock and data recovery (CDR) circuit;
- and
- performing on said clock source signal received at said serial data input of said CDR circuit a CDR operation with said CDR circuit, which produces a desired clock signal in response to said clock source signal.
1 more element
A serial data transceiver apparatus, comprising:
- means for deserializing an input serial data stream;
- means for converting parallel data into an output serial data stream based on a transmit serialization clock signal;
- and
- means for producing said transmit serialization clock signal by applying a clock and data recovery (CDR) operation with a CDR circuit to a clock source signal supplied to a serial data input of said CDR circuit.
1 more element
A serial data transceiver apparatus, comprising:
- a receive data input for receiving an input serial data stream;
- a clock and data recovery (CDR) circuit coupled to said receive data input for recovering a receive clock signal form said input serial data stream;
- a data serializer for converting parallel data into an output serial data stream, said data serializer having a clock input for receiving a transmit serialization clock signal, said data serializer for producing said output serial data stream based on said transmit serialization clock signal;
- a clock synthesizer apparatus coupled to said clock input for providing said transmit serialization clock signal;
- said CDR circuit and said clock synthesizer apparatus having respective PLL clock inputs, each said PLL clock input for receiving first and second PLL clocks;
- and
- a PLL having an output for providing said first and second PLL clocks, said CDR circuit and said clock synthesizer apparatus each having said PLL clock input thereof coupled to said PLL output for receiving said first and second PLL clocks.
4 more elements
A serial data transceiver apparatus, comprising:
- means for providing first and second PLL clocks;
- means for recovering a received clock signal from an input serial data stream based on said first and second PLL clocks;
- means for producing a transmit serialization clock signal based on said first and second PLL clocks;
- and
- means for converting parallel data into an output serial data stream based on said transmit serialization clock signal.
2 more elements
A method of transmitting and receiving serial data, comprising:
- providing first and second PLL clocks;
- recovering a receive clock signal from an input serial data stream based on said first and second PLL clocks;
- producing a transmit serialization clock signal based on said first and second PLL clocks;
- and
- converting parallel data into an output serial data stream based on the transmit serialization clock signal.
2 more elements
Dependencies are inferred from the claim text.