US 7,480,347 B2Granted

Analog front-end having built-in equalization and applications thereof

AssigneeXilinx, Inc.

InventorsWilliam C. Black, Charles W. Boecker, Eric D. Groen

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Abstract

An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Claims12

Dependent claims

An analog front-end having built-in equalization, the analog front-end comprises:

control module operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front end;
and
tunable gain stage operably coupled to amplify and equalize the high-speed serial data based on the frequency response setting, wherein the tunable gain stage comprises:
a frequency dependent load that is adjusted based on the frequency response setting;
amplifier input section operably coupled to the frequency dependent load, wherein the amplifier input section receives the high-speed serial data and, in conjunction with the frequency dependent load amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data;
a first stage operably coupled to amplify and equalize, to a first level, the high-speed serial data based on the frequency response setting to produce a first amplified and equalized serial data;
and
a second stage operably coupled to amplify and equalize the first amplified and equalized serial data based on the frequency response setting to produce the amplified and equalized serial data, the second stage comprising:
an input stage operably coupled to amplify and equalize the first amplified and equalized serial data based on the frequency response setting to produce intermediate amplified and equalized serial data;
and
an output stage operably coupled to amplify and equalize the intermediate amplified and equalized serial data based on the frequency response setting to produce the amplified and equalized serial data.

8 more elements

A high-speed data receiver comprises:

an analog front-end operably coupled to amplify and equalize high-speed data to produce amplified and equalized high-speed data;
and
a clock and data recovery module operably coupled to recover a clock signal and data from the amplified and equalized high-speed data, wherein the analog front-end includes:
a control module operably coupled to provide a frequency response setting based on a channel response of a channel providing the high-speed data to the analog front end;
and
a tunable gain stage operably coupled to amplify and equalize the high-speed data based on the frequency response setting, wherein the tunable gain stage includes:
a frequency dependent load that is adjusted based on the frequency response setting and comprises at least one high pass filter, the at least one high pass filter comprising:
a transistor having a gate, a drain, and a source;
and
an adjustable resistor operably coupled to the gate and the drain of the transistor, wherein a resistance value of the adjustable resistor is set based on the frequency response setting, and wherein parasitic capacitance of the transistor and the adjustable resistor establish a corner frequency for the each of the at least one high pass filter;
and
an amplifier input section operably coupled to the frequency dependent load, wherein the amplifier input section receives the high-speed data and, in conjunction with the frequency dependent load amplifies and equalizes the high-speed data to produce an amplified and equalized serial data.

9 more elements

Dependencies are inferred from the claim text.