Loading patent…
AssigneeInternational Business Machines Corporation
InventorsGerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
Estimating the term…
A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port. The memory chip is incorporated into a design structure that is embodied in a computer readable medium used for designing, manufacturing, or testing the memory chip.
A design structure, for a memory chip, the design structure for the memory chip memory chip comprising:
Dependencies are inferred from the claim text.