Semiconductor memory device and driving method of semiconductor memory device

A semiconductor memory device comprising:

• memory cells including floating bodies in an electrically floating state and storing data based on a number of majority carriers within the floating bodies;
• word lines connected to gates of the memory cells;
• local bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells;
• global bit lines respectively provided corresponding to a plurality of the local bit lines;
• first transfer gates connected to between the global bit lines and the local bit lines;
• sense nodes connected to the global bit lines and transmitting data of the memory cells;
• second transfer gates connected to between the global bit lines and the sense nodes;
• and
• latch circuits latching data to the sense nodes, wherein
• in a data read operation, the first transfer gates between selection local bit lines and the global bit lines are set to off during a latch period from immediately before the latch circuits start a data latch operation until when the second transfer gates disconnect the global bit lines from the sense nodes after the latch operation, the selection local bit lines being included in the local bit lines and being connected to selection memory cells from which data is to be read.

A driving method of a semiconductor memory device, which comprises memory cells including floating bodies in an electrically floating state and storing data based on a number of majority carriers within the floating bodies;

• word lines connected to gates of the memory cells;
• bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells;
• sense nodes connected to the bit lines and transmitting data of the memory cells;
• transfer gates connected to between the bit lines and the sense nodes;
• and latch circuits latching data to the sense nodes,
• the driving method comprising:
• activating a selection word line during a sense period in which data of selection memory cells is detected, the selection word line being one of the word lines and being connected to the selection memory cells from which data is to be read;
• inactivating the selection word line during a latch period from immediately before the latch circuits start a data latch operation until when the transfer gates disconnect the bit lines from the sense nodes after the latch operation;
• and
• activating the selection word line during a restore period in which the latch circuits write back latched data into the selection memory cells.