Implementing calibration of DQS sampling during synchronous DRAM reads
AssigneeInternational Business Machines Corporation
InventorsMichael Joseph Carnevale, Daniel Frank Moertl
Life of this patent
Estimating the term…
Abstract
A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data mask (DQM) IO during a DRAM read for calibration testing. The received DQS signal and the internal Enable signal are used to adjust the Enable delay to generally center the preamble time at the DQS receiver.
Claims17
A method for implementing calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads, said method comprising:
- providing a calibration control to enable calibration testing;
- driving a selected one of a received DQS signal and an internal Enable signal onto a data mask (DQM) IO during a DRAM read for calibration testing;
- and
- responsive to the received DQS signal and the internal Enable signal, adjusting an Enable delay to substantially center a preamble time of the DQS at a DQS receiver.
Apparatus for implementing calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads comprising:
- a calibration control to enable calibration testing;
- a first multiplexer responsive to said calibration control driving a selected one of a received DQS signal and an internal Enable signal onto a data mask (DQM) IO during a DRAM read for calibration testing;
- and
- an Enable delay being adjusted responsive to the received DQS signal and the internal Enable signal to substantially center a preamble time of the DQS at a DQS receiver.
A synchronous dynamic random access memory (SDRAM) system for implementing calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads comprising:
- a memory controller;
- a DRAM module coupled to said memory controller over a source synchronous communications interface;
- said DRAM module including a driver driving the data strobe signal (DQS) during DRAM reads;
- said memory controller including a DQS receiver receiving the data strobe signal (DQS) during DRAM reads;
- said memory controller including DQS receive logic coupled to said DQS receiver including;
- a calibration control to enable calibration testing;
- a first multiplexer responsive to said calibration control driving a selected one of a received DQS signal and an internal Enable signal onto a data mask (DQM) IO during a DRAM read for calibration testing;
- and
- an Enable delay being adjusted responsive to the received DQS signal and the internal Enable signal to substantially center a preamble time of the DQS at a DQS receive.
Dependencies are inferred from the claim text.