Internal data comparison for memory testing

A method of testing a memory device, comprising:

• loading data values into an array of memory cells of the memory device, the array arranged in rows and columns;
• reading data values for a plurality of columns of the array corresponding to a first level of decoding;
• loading data values into a plurality output latches corresponding to expected data values for the plurality of columns;
• comparing the data values for the first plurality of columns with their expected data values, wherein the comparison is performed in the data path between the array and the output latches;
• if any mismatch is detected between the data values for the first plurality of columns and their expected data values, comparing data values for a first subset of the first plurality of columns with their expected data values, wherein the first subset of columns corresponds to a second level of decoding and wherein the comparison for the second level of decoding is performed in the data path between the array and the output latches at a point different from the comparison for the first level of decoding.

A method of testing a memory device, comprising:

• loading a known pattern of data to an array of memory cells of the memory device;
• sensing data values for a first plurality of memory cells associated with a first plurality of columns of the memory array corresponding to a first address value of a first level of decoding;
• latching the sensed data values in a plurality of first latches;
• latching data values in a plurality of second latches from a source other than the memory array, wherein the second latches have a one-to-one correspondence with the first latches, wherein each first and second latch is part of a data path of the memory device for providing data values from the first latch to the second latch during a normal read operation, and wherein the data value for each second latch is the expected data value for its corresponding first latch;
• comparing the data value of each first latch with the data value of its corresponding second latch;
• indicating a defect if any first latch contains a different data value than its corresponding second latch;
• and
• storing the first address value in a register for use by redundancy select circuitry of the memory device if a defect is indicated.

A method of repairing a memory device, comprising:

• loading data values into an array of memory cells of the memory device, the array arranged in rows and columns;
• reading data values for a plurality of columns of the array;
• loading data values into a plurality of output latches from a source other than the array, the data values loaded into the plurality of output latches corresponding to expected data values for the plurality of columns;
• comparing the data values read from the array with their expected data values, wherein the comparison is performed at a point in the data path that is located between the array and the output latches and located between complementary legs of the data path;
• indicating a defect if a mismatch is detected in comparing the data values read from the array with their expected data values;
• storing column addresses corresponding to columns where a mismatch is detected;
• and
• directing access requests to the stored column addresses to redundant columns.