Memory component with multiple delayed timing signals
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory component having multiple delayed timing signals. Control information specifying a write operation and write data corresponding to the write operation are each received via a separate external signal path. A timing signal is received indicating that the write data is valid write data. Signals corresponding to multiple delayed versions of the timing signal are output for use in determining a propagation delay time between the control information and the write data.
Claims20
A method of operation in a memory component having a memory core, the method comprising:
- receiving, via a first external signal path, control information that specifies a write operation;
- receiving, via a second external signal path, data corresponding to the write operation;
- during a calibration operation, receiving a plurality of delayed versions of a timing signal, wherein a rising edge transition of the timing signal indicates a valid first symbol of write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data;
- and
- outputting signals corresponding to the plurality of delayed versions of the timing signal.
A method of operation in a memory component having a memory core, the method comprising:
- receiving, from a first external signal path, control information that specifies a write operation,
- receiving, from a second external signal path, data corresponding to the write operation;
- receiving a timing signal, wherein a rising edge transition of the timing signal indicates a valid first symbol of write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data;
- during a calibration mode receiving a plurality of delayed versions of the timing signal;
- and
- outputting signals corresponding to the plurality of delayed versions of the timing signal.
A method of operation in a memory component having a memory core, the method comprising:
- receiving, via a first external signal path, a plurality of control signals that specify respective write operations;
- receiving, via a second external signal path, data signals corresponding to the write operations;
- receiving a plurality of delayed versions of a timing signal, wherein a rising edge transition of the timing signal indicates a valid first symbol of write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data;
- and
- sampling the data signals corresponding to the write operations in response to the plurality of delayed versions of the timing signal, wherein a different one of the delayed versions of the timing signal is used for each of the write operations.
Dependencies are inferred from the claim text.