Pull-up voltage circuit
AssigneeXilinx, Inc.
InventorHuy Son Nguyen
Life of this patent
Estimating the term…
Abstract
A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a first output node of the inverter to a first input node. A source region of the n-type transistor is coupled to a ground. A drain region of each of the first p-type transistor and the n-type transistor are commonly coupled at a second output node. A second p-type transistor has a gate coupled to the second output node. A drain region of the second p-type transistor, a source region of the first p-type transistor, and an input of the inverter are all coupled to a line. A source region of the second p-type transistor is coupled to the first supply voltage.
Claims7
A memory device having an array of memory cells including bitlines and wordlines, comprising:
- voltage pull-up circuits for precharging the bitlines;
- the voltage pull-up circuits operating with a first supply voltage level;
- the array of memory cells operating with a second supply voltage level greater than the first supply voltage level;
- wherein each voltage pull-up circuit is configured to:
- sense voltage on the respective bitline;
- precharge the respective bitline responsive to voltage on the respective bitline exceeding a trip voltage associated with the voltage pull-up circuit;
- and
- cease precharging responsive to voltage on the respective bitline exceeding a reverse bias voltage, the reverse bias voltage being greater than the trip voltage and less than the first supply voltage level.
Dependencies are inferred from the claim text.