Known default data state EPROM

An EPROM comprising:

• a first transistor coupled to a first voltage potential;
• a second transistor coupled to the first voltage potential;
• a latching circuit coupled to the first transistor and the second transistor, wherein the latching circuit outputs a first output value when the current through the first transistor is greater than the current through the second transistor and outputs a second output value when the current through the first transistor is less than the current through the second transistor;
• a first capacitive element coupled between a gate of the first transistor and a third voltage potential, the capacitance of the first capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM;
• and
• a second capacitive element coupled between a gate of the second transistor and a fourth voltage potential, the capacitance of the second capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM.

A method for signaling the program status of an EPROM, the method comprising:

• outputting a pre-defined first digital state at a program status bit prior to programming, wherein the first digital state indicates that the EPROM has not been programmed;
• receiving a programming signal at an input of the EPROM;
• outputting a pre-defined second digital state at the program status bit in response to the programming signal being asserted at the input of the EPROM, wherein the second digital state indicates that the ERPOM has been programmed;
• capacitively coupling a gate of a first transistor of the EPROM to a first voltage potential such that the EPROM is guaranteed to output the first digital state at the program status bit prior to programming and the second digital stage after programming;
• and
• capacitively coupling a gate of the second transistor to a second voltage potential such that the EPROM is guaranteed to output the first digital state at the program status bit prior to programming and the second digital stage after programming.