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US 7,480,189 B2Granted
Cross-coupled write circuit
AssigneeIntel Corporation
InventorsLawrence T. Clark, Jay B. Miller
Life of this patent
Estimating the term…
Abstract
A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.
Claims5
A memory comprising:
- a sense amp coupled to first and second global bit lines;
- and
- memory cells arrayed in a column and coupled to first and second local bit lines to receive data respectively supplied from the first global bit line through a first non-inverting buffer and the second global bit line through a second non-inverting buffer that includes an inverter having an input coupled to the second global bit line and a transistor having a gate coupled to an output of the inverter and having a current conduction terminal coupled to the second local bit line.
A cache having memory cells, comprising:
- a sense amp coupled to first and second global bit lines;
- and
- first and second bit lines local to a group of the memory cells that couple the group of memory cells to the first and second global bit lines to make the memory cells readable and writeable to the sense amp;
- wherein data on the first global bit line is buffered by a first buffer and provided on the first local bit line to the group of memory cells and complemented data on the second global bit line is buffered by a second buffer and provided on the second local bit line to the group of memory cells.
1 more element
Dependencies are inferred from the claim text.