Nonvolatile semiconductor memory with low-loading bit line architecture and method of programming the same

For a NAND flash memory device comprising an array of NAND flash memory cells arranged in a plurality of word lines and a plurality of bit lines, the bit lines each comprising a first bit line portion, a second bit line portion, and a switching device extending between the first and second bit line portions to selectively connect the first and second bit line portions, and further comprising a first page buffer connected to the first bit line portions and a second page buffer connected to the second bit line portions, a method of programming the NAND flash memory cells, comprising:

• loading into the primary page buffer second data to be programmed into second NAND flash memory cells connected to the second bit line portions;
• transferring the second data from the primary page buffer to the secondary page buffer;
• loading into the primary page buffer first data to be programmed into first NAND flash memory cells connected to the first bit line portions;
• controlling the switching devices to disconnect the first and second portions of the bit lines from each other;
• and
• programming the first NAND flash memory cells with the first data of the primary page buffer while programming the second NAND flash memory cells with the second data of the secondary page buffer.