NROM flash memory with self-aligned structural charge separation

A non-volatile memory device comprising:

• control circuitry for controlling operation of the memory device;
• and
• a memory array coupled to the control circuitry and comprising a plurality of non-volatile, NROM cells formed on a substrate, each cell comprising:
• first and second source/drain regions formed laterally in the substrate such that a channel area is formed between them;
• an oxide layer on the substrate above the first and second source/drain regions and the channel area;
• a gate insulator layer comprising a first section and a separate second section that does not connect to the first section, a substantially horizontal portion of the first and second sections coupled to separate areas of the oxide layer;
• and
• a gate structure comprising a middle section and first and second outer sections, the middle section coupled to the oxide layer and separating the first and second gate insulator sections, the first and second outer sections each separated from any contact with the middle section by the first and second sections, respectively, of the gate insulator.

A non-volatile memory device comprising:

• control circuitry for controlling operation of the memory device;
• and
• a memory array coupled to the control circuitry and comprising a plurality of non-volatile, NROM cells formed on a substrate, each cell comprising:
• first and second source/drain regions formed laterally in the substrate such that a channel area is formed between them;
• an oxide layer on the substrate above the first and second source/drain regions and the channel area;
• a composite gate insulator layer comprising a first section and a separate second section that is not in contact with the first section, a substantially horizontal portion of each section coupled to separate areas of the oxide layer and a substantially vertical portion of each section extending from the oxide layer, the composite gate insulator layer having a nitride layer for storing a charge on each of the first and second sections;
• a polysilicon gate structure comprising a middle section and first and second outer sections, the middle section coupled to the oxide layer and separated from any contact with the first and second outer sections by the substantially vertical portions of the gate insulator layer;
• and
• a gate metal contact coupled to the outer and middle sections of the gate structure and each of the substantially vertical portions of the gate insulator.

A method for fabricating an NROM memory device, the method comprising:

• forming first and second source/drain regions in a substrate for each memory cell of a plurality of memory cells, the first and second source/drain regions positioned laterally on the substrate and separated by a channel area;
• depositing an oxide layer over the substrate including the first and second source/drain regions and the channel area;
• forming a polysilicon middle gate region on the oxide layer above the channel area for each memory cell;
• depositing a gate insulator layer over the oxide layer;
• depositing a polysilicon layer over the gate insulator layer;
• etching the polysilicon layer for each memory cell such that two outer gate regions are left from the polysilicon layer thus forming a gate structure with a middle gate region and two outer gate regions separated from the middle by the gate insulator layer;
• planarizing a top of the gate structure of each memory cell such that the gate insulator layer is removed from the top of the gate structure;
• and
• forming a contact over the gate structure of each memory cell that is coupled to each region of the gate structure and remaining end portions of the gate insulator layer.

A method for fabricating an NROM memory device, the method comprising:

• forming first and second source/drain regions in a substrate for each memory cell of a plurality of memory cells, the first and second source/drain regions positioned laterally on the substrate and separated by a channel region;
• forming a composite insulator over the substrate including the first and second source/drain regions and the channel region, the composite insulator having a lower oxide layer;
• forming a polysilicon middle gate region on the lower oxide layer above the channel region for each memory cell;
• forming a gate structure with the middle gate region wherein two outer gate regions are separated from any contact with the middle gate region by at least two layers of the composite insulator;
• and
• forming a contact on the gate structure of each memory cell, the contact coupled to each region of the gate structure and end portions of the at least two layers of the composite insulator.