Semiconductor memory device, and read method and read circuit for the same
AssigneePanasonic Corporation
InventorToshiki Mori
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation. The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line. Upon completion of the read of the memory cell, the selected bit line is disconnected from the read circuit and reset to thereby complete discharge of residual charge in the read bit line prior to read operation in the next cycle. This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.
Claims29
A read method for a semiconductor memory device comprising a plurality of word lines and a plurality of bit lines, memory cells being placed at respective intersections between the plurality of word lines and the plurality of bit lines, the bit lines being put in a reset state at all times except during read operation, the method comprising the steps of:
- canceling the reset state of a bit line only during the time when the bit line is selected for readout and connected to a read circuit;
- reading information stored in a selected memory cell via the selected bit line;
- and
- disconnecting the selected bit line from the read circuit and resetting the selected bit line after completion of the readout of the selected memory cell.
A read method for a semiconductor memory device comprising a plurality of word lines and a plurality of bit lines, memory cells being placed at respective intersections between the plurality of word lines and the plurality of bit lines, the bit lines being put in a reset state at all times except during read operation, the method comprising the steps of:
- selectively connecting a bit line to a read circuit in response to an input address;
- canceling the reset state of the bit line selectively connected to the read circuit in response to the input address;
- reading information stored in a selected memory cell via the selected bit line;
- and
- disconnecting the selected bit line from the read circuit and resetting the selected bit line after completion of the readout of the selected memory cell.
A read circuit for a semiconductor memory device comprising a plurality of word lines and a plurality of bit lines, memory cells being placed at respective intersections between the plurality of word lines and the plurality of bit lines, the read circuit comprising:
- a bit line reset circuit for resetting the bit lines at all times except during read operation;
- a selection signal generation circuit for generating a bit line selection signal in response to an input address;
- a connection circuit for selectively connecting a bit line to the read circuit according to the bit line selection signal;
- a bit line reset cancellation circuit for canceling the reset state of the bit line selectively connected to the read circuit according to the bit line selection signal;
- and
- a read determination circuit for reading information stored in a selected memory cell via the selected bit line.
A semiconductor memory device comprising a plurality of word lines and a plurality of bit lines, memory cells being placed at respective intersections between the plurality of word lines and the plurality of bit lines, the device comprising:
- a row decoder for selecting a particular word line among the plurality of word lines in response to an input address;
- a column decoder for outputting a bit line selection signal for selecting a particular bit line among the plurality of bit lines in response to another input address;
- a read circuit for reading information stored in a selected memory cell;
- a column selection circuit for selectively connecting a particular bit line among the plurality of bit lines to the read circuit according to the bit line selection signal from the column decoder;
- and
- a switch circuit for controlling the conduction state between the bit line and a reference potential according to the bit line selection signal from the column decoder.
A semiconductor memory device comprising a plurality of word lines and a plurality of bit lines, memory cells being placed at respective intersections between the plurality of word lines and the plurality of bit lines, the device comprising:
- a row decoder for selecting a particular word line among the plurality of word lines in response to an input address;
- a column decoder for outputting a bit line selection signal for selecting a particular bit line among the plurality of bit lines in response to another input address;
- a read circuit for reading information stored in a selected memory cell;
- a first column selection circuit for selecting a particular bit line among the plurality of bit lines according to the bit line selection signal from the column decoder;
- a second column selection circuit for selectively connecting the output of the first column selection circuit to the read circuit according to the bit line selection signal from the column decoder;
- and
- first and second switch circuits for controlling the conduction state between the bit line and a reference potential according to the bit line selection signal from the column decoder.
Dependencies are inferred from the claim text.