Ideal CMOS SRAM system implementation

The memory system hereby comprises a plurality of SRAM memory groups (28) arranged in rows and columns and formed on a substrate assembly comprising at least one semiconductor layer;

• at least one memory group (28) is coupled to both an internal supply line (1) and an internal ground line (2) where the said internal supply line (1) and the said internal ground line (2) are implemented on a chip together with the said memory group/s (28);
• a memory group (28) comprises one or more SRAM memory cells (15, 16, 17) together with supply switch select FETs (24, 25, 26, 27);
• an SRAM memory cell comprises two cascaded inverters together with two switch select FETs (18 and 19), where each of the said inverters output is coupled to the other inverter input, wherein each of the said inverters comprises a PFET (20, 21) with its drain coupled to the drain of an NFET (22, 23) and both drains are coupled to the output terminal of the inverter they constitute, the said NFET gate is coupled to the said PFET gate, and both are coupled to the input terminal of the inverter they constitute;
• the input terminal of an inverter stage is coupled to the first terminal of a switch select FET (18) while the input of the other inverter stage is coupled to the first terminal of another switch select FET (19);
• two or more of the said Supply switch select FETs (24, 25) are formed so that their Drains are coupled together while their sources are coupled together, the aggregate of Source to Drain junctions couple between the sources of the PFETs (20, 21) of one or more of the said SRAM memory cells and the said internal supply line (1), while two or more of the said Supply switch select FETs (26, 27) are formed so that their Drains are coupled together while their Sources are coupled together, the aggregate of Source to Drain junctions couple between the Sources of the NFETs (22, 23) of one or more of the said SRAM memory cells and the said internal ground line (2), and
• the memory system comprises a plurality of control lines wherein the Gate of each of the said supply switch select FETs (24, 25, 26, 27) is connected to a separate control line (3, 4, 5, 6) where each signal applied to a control line (3, 4, 5, 6) is used to specify a spatial address selection, being a row address, a column address, or any other dimensional address, which enables a random access of one or more memory cells, and each of the supply switch select FETs (24, 25, 26, 27) operates in either “ON” status during which its source to drain resistance is intended to be as low as possible aiming at keeping the data storing points inside memory cells connected to strong supply nodes, or in “OFF” status during which its source to drain resistance is intended to be as high as possible so as to Omit connectivity between the memory cells and both the internal Supply line (1) and the internal Ground line (2) for the changing cells during a write cycle, and to be insufficient to keep the stored data inside memory cells, and
• data is entered via both switch select FETs (18, 19) of a memory cell simultaneously during a write cycle, where a bit is entered via a first switch select FET while its complement is entered via the second switch select FET, and each terminal of each FET, PFET, NFET is coupled to a corresponding wiring line formed on a chip.