On chip real time FPN correction without imager size memory
AssigneeDigital Imaging Systems GmbH
InventorTaner Dosluoglu
Life of this patent
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AssigneeDigital Imaging Systems GmbH
InventorTaner Dosluoglu
Estimating the term…
A circuit and method for correcting pixel output signals for fixed pattern noise. Pixels in a selected row of pixels are read after an integration period and the resulting signals are stored in a first sample and hold circuit for each column. The pixels in the selected row are then reset and immediately read again and the resulting signals are stored in a second sample and hold circuit for each column. The signals in the second sample and hold circuits are subtracted from the signals in the first sample and hold circuits to produce signals related to the light seen by the pixels in the selected row corrected for fixed pattern noise. The output of the first sample and hold circuits and second sample and hold circuits can be connected to a subtraction unit and sequentially activated so that a single subtraction unit is required for the entire imager. The output of the subtraction unit can connected to a buffer thereby storing signals corrected for fixed pattern noise in the buffer using only a single subtraction unit and avoiding the need for a large memory to store dark pixel signals.
A method of correcting for fixed pattern noise, comprising:
A method of correcting for fixed pattern noise in an imager:
A circuit for correcting for fixed pattern noise in an imager:
Dependencies are inferred from the claim text.