US 7,479,941 B2Granted

Display element drive apparatus and image display apparatus

AssigneePanasonic Corporation

InventorsKazuya Matsumoto, Yasuyuki Doi

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Abstract

In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

Claims17

Dependent claims

A display element drive apparatus for driving a display element formed on a display panel, comprising:

a first comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first clock signal and a second clock signal, the first clock signal is input to the positive-phase input terminal, and the second clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first clock signal and the second clock signal is output as a first reference clock signal;
a second comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second clock signal is input to the positive-phase input terminal and the first clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second clock signal and the first clock signal is output as a second reference clock signal;
a first hold circuit of holding a data signal input in synchronization with the first reference clock signal;
a second hold circuit of holding a data signal input in synchronization with the second reference clock signal;
a third comparator, wherein a differential signal includes a pair of a first data signal and a second data signal, and a voltage signal corresponding to a potential difference between the first data signal and the second data signal is output as the data signal;
and
a delay circuit of delaying the data signal output by the third comparator,
wherein the first hold circuit receives the data signal delayed by the delay circuit, and the second hold circuit receives the data signal delayed by the delay circuit.

5 more elements

A display element drive apparatus for driving a display element formed on a display panel, comprising:

a first comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first clock signal and a second clock signal, the first clock signal is input to the positive-phase input terminal, and the second clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first clock signal and the second clock signal is output as a first reference clock signal;
a second comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second clock signal is input to the positive-phase input terminal and the first clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second clock signal and the first clock signal is output as a second reference clock signal;
a first hold circuit of holding a data signal input in synchronization with the first reference clock signal;
a second hold circuit of holding a data signal input in synchronization with the second reference clock signal;
a third comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first data signal and a second data signal, the first data signal is input to the positive-phase input terminal, and the second data signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first data signal and the second data signal is output;
a fourth comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second data signal is input to the positive-phase input terminal and the first data signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second data signal and the first data signal is output;
a first delay circuit of delaying the signal output by the third comparator and outputting the delayed signal as a data signal for the first hold circuit, and
a second delay circuit of delaying the signal output by the fourth comparator and outputting the delayed signal as a data signal for the second hold circuit.

5 more elements

An image display apparatus comprising:

a display panel comprising a plurality of image display elements;
a plurality of display element drive apparatuses for driving the image display element on the display panel, and
a control circuit for controlling operations of the plurality of display element drive apparatuses,
wherein at least one of the plurality of display element drive apparatuses comprises:
a first comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first clock signal and a second clock signal, the first clock signal is input to the positive-phase input terminal, and the second clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first clock signal and the second clock signal is output as a first reference clock signal;
a second comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second clock signal is input to the positive-phase input terminal and the first clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second clock signal and the first clock signal is output as a second reference clock signal;
a first hold circuit of holding a data signal input in synchronization with the first reference clock signal;
a second hold circuit of holding a data signal input in synchronization with the second reference clock signal;
a third comparator, wherein a differential signal includes a pair of a first data signal and a second data signal, and a voltage signal corresponding to a potential difference between the first data signal and the second data signal is output as the data signal;
and
a delay circuit of delaying the data signal output by the third comparator,
wherein the first hold circuit receives the data signal delayed by the delay circuit, and the second hold circuit receives the data signal delayed by the delay circuit.

9 more elements

An image display apparatus comprising:

a display panel comprising a plurality of image display elements;
a plurality of display element drive apparatuses for driving the image display element on the display panel, and
a control circuit for controlling operations of the plurality of display element drive apparatuses,
wherein at least one of the plurality of display element drive apparatuses comprises:
a first comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first clock signal and a second clock signal, the first clock signal is input to the positive-phase input terminal, and the second clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first clock signal and the second clock signal is output as a first reference clock signal;
a second comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second clock signal is input to the positive-phase input terminal and the first clock signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second clock signal and the first clock signal is output as a second reference clock signal;
a first hold circuit of holding a data signal input in synchronization with the first reference clock signal;
and
a second hold circuit of holding a data signal input in synchronization with the second reference clock signal;
a third comparator having a positive-phase input terminal and a negative-phase input terminal, wherein a differential signal includes a pair of a first data signal and a second data signal, the first data signal is input to the positive-phase input terminal, and the second data signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the first data signal and the second data signal is output;
a fourth comparator having a positive-phase input terminal and a negative-phase input terminal, wherein the second data signal is input to the positive-phase input terminal and the first data signal is input to the negative-phase input terminal, and a voltage signal corresponding to a potential difference between the second data signal and the first data signal is output;
a first delay circuit of delaying the signal output by the third comparator and outputting the delayed signal as a data signal for the first hold circuit, and
a second delay circuit of delaying the signal output by the fourth comparator and outputting the delayed signal as a data signal for the second hold circuit.

10 more elements

Dependencies are inferred from the claim text.