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US 7,479,913 B1Granted
Configurable analog to digital converter
AssigneeCypress Semiconductor Corporation
InventorsEashwar Thiagarajan, Bert Sullam
Life of this patent
Estimating the term…
Abstract
A configurable analog to digital converter (ADC) includes a plurality of analog units to integrate an input signal. The analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal and are further coupled to a plurality of bus segments via a plurality of interconnect circuits. Each interconnect circuit is configured to selectively couple the analog units to any of the bus segments.
Claims19
An apparatus comprising:
- a plurality of analog units to integrate an input signal, wherein the plurality of analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal;
- a plurality of bus segments to propagate at least one of the plurality of discrete-time signals;
- and
- a plurality of interconnect circuits to selectively couple the plurality of analog units to any of the plurality of bus segments, wherein the plurality of interconnect circuits includes a plurality of feedback multiplexers (MUXs) coupled between the plurality of bus segments and the plurality of analog units to couple any of the plurality of bus segments to the plurality of analog units to feedback any of the plurality of discrete-time signals.
1 more element
A method comprising:
- configuring a plurality of interconnect circuits coupled between a plurality of analog units and a plurality of bus segments to selectively output a plurality of discrete-time signals onto any of the plurality of bus segments, wherein the plurality of analog units are configured to generate the plurality of discrete-time signals responsive to an input signal;
- and
- configuring the plurality of interconnect circuits to selectively feedback any of the plurality of discrete-time signals to any of the plurality of analog units, wherein configuring the plurality of interconnect circuits to selectively feedback any of the plurality of discrete-time signals to any of the plurality of analog units includes configuring a plurality of feedback multiplexers (MUXs) coupled between the plurality of bus segments and the plurality of analog units.
A system comprising:
- a plurality of analog units coupled together to form an analog-to-digital converter (ADC) having a plurality of orders of analog integration, wherein the plurality of analog units generate a plurality of discrete-time signals responsive to an analog input signal;
- a plurality of bus segments to propagate at least one of the plurality of discrete-time signals;
- a plurality of interconnect circuits coupled between the plurality of analog units and the plurality of bus segments to selectively couple the plurality of analog units to any of the plurality of bus segments, wherein the plurality of interconnect circuits includes a plurality of feedback multiplexers (MUXs) coupled between the plurality of bus segments and the plurality of analog units to couple any of the plurality of bus segments to the plurality of analog units to feedback any of the plurality of discrete-time signals;
- and
- a processor coupled to configure the plurality of interconnect circuits to select any one of the plurality of orders of analog integration.
2 more elements
Dependencies are inferred from the claim text.