Low-power high-performance audio DAC system including internal oscillator, FIFO memory, and ASRC

A method for reducing power consumption required for converting a serial digital data input signal to an analog output signal, the method comprising:

• (a) generating the serial digital data input signal at a first sample rate in a burst mode, wherein the serial digital data input signal has a predetermined rate ratio to an external reference clock signal;
• (b) converting the burst mode serial digital data input signal into parallel format, the digital processor being in a high power mode while generating the serial digital data input signal in the burst mode, the digital processor being in a low power mode during at least some of the time during which the digital processor is not generating the serial digital data input signal;
• (c) temporarily storing a predetermined number of samples of the parallel format digital data input signal in a FIFO system, the samples having a first sample rate;
• (d) converting the samples to an analog output signal;
• and
• (e) establishing timing of various clock signals for the serial interface circuit, FIFO system, and audio DAC based on a particular clock signal.

A low-power data conversion system for converting a serial digital data input signal to an analog output signal, comprising:

• (a) means for generating the serial digital data input signal at a first sample rate in a burst mode, wherein the serial digital data input signal has a predetermined rate ratio to an external reference clock signal;
• (b) means for converting the burst mode serial digital data input signal into parallel format, the digital processor being in a high power mode while generating the serial digital data input signal in the burst mode, the digital processor being in a low power mode during at least some of the time during which the digital processor is not generating the serial digital data input signal;
• (c) FIFO means for temporarily storing a predetermined number of samples of the parallel format digital data input signal, the samples having a first sample rate;
• (d) means for converting the samples to an analog output signal;
• and
• (e) means for establishing timing of various clock signals for the serial interface circuit, FIFO means, and audio DAC based on a particular clock signal.