Filter driven DC-free code

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the signal buffer based on the invert signal such that an average DC value of the data approaches zero, wherein the data includes past encoder outputs and possible future encoder outputs.

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero, wherein the inverter bit includes at least two inverter bits.

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero, wherein the metric includes a maximum of an absolute value of a running digital sum.

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero, wherein the DC-Check circuit includes limiting a maximum DC offset of a filtering operation.

An encoder, comprising:

• a buffer that buffers data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit, responsive to the invert signal, that controls an inverter bit of an output of the buffer such that an average DC value of the data approaches zero, wherein the metric includes a maximum DC offset for a DC correction circuit.

An encoder, comprising:

• a buffer that buffers data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• an inverter unit, responsive to the invert signal, that controls an inverter bit of an output of the buffer such that an average DC value of the data approaches zero, wherein the DC-Check circuit includes limiting for a DC correction circuit:
• a low pass filter to model the DC correction circuit;
• and
• an offset estimation filter.

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero,
• wherein the DC-Check circuit includes threshold limiting based on a number of times the metric is at least one of above and below a threshold.

An encoder, comprising:

• a buffer that stores data associated with a communication signal;
• a DC-Check circuit that computes a metric as a function of the data;
• a DC tracking block that generates an invert signal as a function of the metric, wherein the invert signal has an inverted state and a non-inverted state;
• and
• an inverter unit that controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero, and wherein the DC-Check circuit includes limiting a maximum DC offset slope change of a running digital sum of the data.