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US 7,479,834 B2Granted
Analogue self-calibration method and apparatus for low noise, fast and wide-locking range phase locked loop
AssigneeMarvell International Ltd.
InventorsAdil Koukab, Michel Declercq
Life of this patent
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Abstract
A phase lock loop (PLL) frequency synthesizer includes a reconfigurable voltage controlled oscillator (VCO) with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During the linear high gain mode, the VCO enables an analogue self-calibration of the PLL over a wide frequency tuning range. Control voltage at the input of the VCO is varied by the PLL to provide an output frequency. When the PLL is locked, the VCO is switched to the Zero-gain mode while maintaining the output.
Claims23
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged;
- generating a control voltage based on said comparing of said output signal and said reference signal;
- and
- offsetting said control voltage to generate an output voltage,
- wherein the tuning voltage is generated based on said output voltage and a reference voltage.
4 more elements
Integrated circuit comprising a phase locked loop circuit including:
- a detector to compare phase and frequency of a reference signal to phase and frequency of an internal feedback signal and to generate output error signals,
- a charge pump to generate amounts of charges proportional to said output error signals,
- a loop filter to set an analogue voltage proportional to charges accumulated in capacitors and based on said amounts of charges,
- a voltage-controlled oscillator with inputs that each correspond to an element tuned by a tuning voltage, and
- a gain mode switcher circuit connected between an output of the loop filter and the inputs, to enable the voltage-controlled oscillator to work successively in a linear high-gain mode and a zero-gain mode, the gain mode switcher circuit including:
- offset generators to generate output voltages after shifting an output voltage of the loop filter with predefined offsets,
- comparators, and
- a switch configuration to apply the output voltages of the offset generators to the inputs of the voltage-controlled oscillator during the linear-high-gain mode, to isolate the inputs of the voltage-controlled oscillator from the offset generators and to apply the output voltages of said offset generators to inputs of the comparators during transition to the zero-gain mode, to apply the resulting outputs voltages of said comparators to the inputs of the voltage-controlled oscillator and to freeze the state of each comparator and output frequency of the voltage-controlled oscillator making the output frequency independent of the output voltage of the loop filter during the zero-gain mode.
5 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- and
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged,
- wherein, after said zero-pain mode, said voltage-controlled oscillator operating mode is switched to a low-pain mode enabling fine tuning of the frequency of the output signal by the phase locked loop circuit to compensate for residual frequency errors and temperature variations, and
- wherein the switching operation of the voltage-controlled oscillator from the zero-gain mode to the low-gain mode comprises:
- using an additional element tuned by the tuning voltage that is dimensioned for fine tuning with a low voltage-controlled oscillator gain;
- linking said additional element tuned by the tuning voltage to a fixed voltage during the linear-high-gain mode and the zero-gain mode;
- isolating said additional element from the fixed voltage during switching from the zero-gain mode to the low-gain mode;
- and
- linking said additional element to the tuning voltage that is supplied by the loop filter of the phase locked loop.
8 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- and
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged,
- wherein, after said zero-gain mode, said voltage-controlled oscillator operating mode is switched to a low-gain mode enabling fine tuning of the frequency of the output signal by the phase locked loop circuit to compensate for residual frequency errors and temperature variations, and
- wherein a loop filter output voltage of the phase locked loop circuit is compared to an upper and a lower limit by means of additional comparators during the low-gain mode;
- and tuning operations are restarted and the linear-high-gain mode is selected when the loop filter output voltage reaches either of the upper limit or the lower limit.
4 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- and
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged,
- wherein, after said zero-gain mode, said voltage-controlled oscillator operating mode is switched to a low-gain mode enabling fine tuning of the frequency of the output signal by the phase locked loop circuit to compensate for residual frequency errors and temperature variations, and
- wherein the phase locked loop stability during the linear-high-gain and the low-gain modes is preserved by decreasing the current of the charge pump during the linear-high-gain mode and by increasing the current of the charge pump during the low-gain mode such that a product of the current of the charge pump and gain of the voltage-controlled oscillator remains constant.
3 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged;
- generating a control voltage based on said comparing of said output signal and said reference signal;
- and
- offsetting said control voltage to generate an output voltage based on said linear frequency versus voltage curve,
- wherein the tuning voltage is generated based on said output voltage and a reference voltage.
4 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged;
- generating a control voltage based on said comparing of said output signal and said reference signal;
- varying offset of said control voltage to generate a plurality of output voltages;
- and
- generating a plurality of tuning voltages based on said plurality of output voltages and a reference voltage.
4 more elements
Method for analogue self calibrating of a phase locked loop circuit including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, including elements tuned by a tuning voltage, the method comprising:
- comparing a frequency of an output signal of the voltage-controlled oscillator of the phase locked loop circuit with a reference signal frequency entering in the phase frequency detector;
- switching a voltage-controlled oscillator operating mode to a linear-high-gain mode to enable a first frequency tuning operation that includes targeting a linear frequency versus voltage curve to vary the frequency of the output signal within a frequency locking range;
- and
- after locking to a frequency with said first frequency tuning operation, switching said voltage-controlled oscillator operating mode to a zero-gain mode while keeping the frequency of the output signal unchanged,
- wherein said zero-gain mode comprises:
- comparing an offset control voltage to a reference voltage;
- and
- setting the tuning voltage to one of a plurality of voltage potentials based on said comparing.
5 more elements
Dependencies are inferred from the claim text.