Clock forming method for semiconductor integrated circuit and program product for the method
AssigneeRenesas Technology Corp.
InventorMichio Komoda
Life of this patent
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Abstract
Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.
Claims5
A clock forming method for a semiconductor integrated circuit comprising the steps of:
- a first step of dividing a circuit region into plural regions, each region having plural elements and connection channels for transferring data between the plurality of regions;
- and
- a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form,
- wherein the number of connection channels intersected by a boundary is minimized when the circuit region is divided, and
- wherein when the circuit region is divided, the positions of the elements contained in each region after dividing are within a predetermined distance from a centroid of the region.
A clock forming method for a semiconductor integrated circuit, the method comprising:
- a first step of dividing a circuit region into plural regions, each region having plural elements and connection channels for transferring data between the plurality of regions;
- a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form;
- wherein the number of connection channels intersected by a boundary is minimized when the circuit region is divided, and
- wherein when the circuit region is divided, the boundary does not intersect the connection channels having a setup margin equal to or smaller than a predetermined value.
A program product for causing a computer to execute a clock forming for a semiconductor integrated circuit:
- a first step of dividing a circuit region into plural regions each region having plural elements and connection channels for transferring data between the regions;
- and
- a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form,
- wherein the number of the connection channels intersected by a boundary is minimized when the circuit region is divided, and
- wherein when the current region is divided, the positions of the elements contained in each region after dividing are within a predetermined distance from the centroid of the region or the boundary does not intersect the connection channels having a setup margin equal to or smaller than a predetermined value.
Dependencies are inferred from the claim text.