Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees

A clock distribution network of an integrated circuit, the clock distribution network comprising:

• a clock source;
• a first distribution level of clock fanout including a first set of buffer circuits and a first set of distribution segments, each of said first plurality of distribution segments connecting said clock source to a corresponding respective one of said first set, each of said first plurality of distribution segments having substantially the same physical and electrical properties, each buffer circuit of said first set having substantially the same load;
• a second distribution level of clock fanout including a second set of buffer circuits and a second plurality of distribution segments, each of said second plurality of distribution segments connecting a buffer circuit of said first set to a buffer circuit of said second set, each buffer circuit of said first set being connected to an equal number of buffer circuits of said second set, each of said second plurality of distribution segments having substantially the same load, each buffer circuit of said second set having substantially the same load;
• a logic leaf distribution level including a plurality of logic leaf connection nodes and a third plurality of distribution segments, each of said third plurality of distribution segments connecting a buffer circuit of said second set to a node of said plurality of logic leaf connection nodes, each buffer circuit of said second set being connected to an equal number of said plurality of logic leaf connection nodes, each of said third plurality of distribution segments having substantially the same physical and electrical properties;
• and
• a plurality of logic leaf elements each connected to a corresponding respective one of said plurality of logic leaf connection nodes, each of said plurality of logic leaf elements having a first load, wherein at least one of said plurality of logic leaf elements includes a dummy register including one or more dummy load elements providing said first load, wherein at least one of said plurality of logic leaf elements includes a logic register having a first number of bits providing said first load.