Back to results
US 7,479,817 B2Granted
Semiconductor device
AssigneePanasonic Corporation
InventorTakashi Yoneda
Life of this patent
Estimating the term…
Abstract
A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.
Claims8
A semiconductor device comprising:
- a memory voltage monitoring circuit generating a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage;
- and
- a reset circuit generating a reset signal from an external reset signal, the external reset signal being generated by an operation voltage monitoring circuit when the power supply voltage drops below an operation voltage of the semiconductor device, and outputting the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal, wherein
- the memory voltage monitoring circuit operates while the reset signal shows operation permission.
1 more element
The semiconductor device according to 3, wherein
- the operation voltage and the memory contents holding voltage have a relation such that the operation voltage > the memory contents holding voltage.
Dependencies are inferred from the claim text.