Generating multiple delayed signals of different phases from a reference signal using delay locked loop (DLL)

A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising:

• a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths based on a strength of a control signal;
• a first control loop controlling said strength of said control signal to cause synchronization of edges of said reference signal with edges of the output of a last one of
• said first plurality of delay elements, said first control loop containing said first plurality of delay elements;
• and
• a second control loop also controlling said strength of said control signal to avoid situations of synchronization of edges of the output of the last one of said plurality of delay elements with edges separated by multiple time periods of said reference signal;
• wherein said second control loop comprises a second plurality of delay elements generating a corresponding plurality of dummy signals, wherein said plurality of delayed signals do not pass through the second plurality of delay elements;
• and
• wherein said second control loop performs said avoiding by determining situations in which a total delay caused by said first plurality of delay elements has crossed an upper threshold.

A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising:

• a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths;
• a duty cycle correction circuit generating a modified signal from said reference signal, said modified signal having a duty cycle different from the duty cycle of said reference signal if the duty cycle of said reference signal is not close to 50%;
• a phase detector comparing a phase of said reference signal and the delayed signal on an output path of a last one of said first plurality of delay elements, and controlling a magnitude of delay caused by each of said first plurality of delay elements at least until edges of said reference signal and the delayed signal are synchronized;
• a second plurality of delay elements also connected in series and receiving said modified signal, said second plurality of delay elements generating a plurality of dummy signals on corresponding second plurality of output paths, wherein a signal path between the reference signal and the delayed signal on said output path does not pass through the second plurality of delay elements;
• and
• a lock detector determining whether a total delay caused by said first plurality of delay elements is more than an upper threshold by examining at least some of said plurality of dummy signals, said lock detector causing said magnitude of said delay to be further decreased if said total delay is more than said upper threshold even if said phase detector otherwise determines that said edges of said reference signal and the delayed signal are synchronized.