Low power three-level detector

A system comprising:

• a pin configured to receive an input signal;
• and
• a detector circuit comprising:
• an input node coupled to the pin;
• first and second diode-connected transistors having respective drain terminals coupled to the input node, wherein the first and second diode-connected transistors are operable to set an intermediate voltage at the input node when the input node is open;
• first and second inverting stages having respective inputs coupled to the input node, wherein the first and second inverting stages are operable to provide an indication of a present state of the input node being one of:
• a high state for a high-level input signal,
• a low state for a low-level input signal, and
• an open state;
• and
• first and second latches having respective outputs, the first latch having an input coupled to an output of the first inverting stage and the second latch having an input coupled to an output of the second inverting stage, wherein the first and second latches are operable to latch the present state of the input node;
• wherein the detector circuit is operable to latch the present state of the input node according to a power-on-reset signal used to power up the system.

A system for detecting an input voltage level, the system comprising:

• an input node configured to receive an input signal;
• first and second diode-connected transistors having respective drain terminals coupled to the input node, wherein the first and second diode-connected transistors are operable to set an intermediate voltage at the input node if the input signal is open;
• first and second inverting stages having respective inputs coupled to the input node, wherein the first and second inverting stages are operable to distinguish whether the input signal is low, high, and/or open;
• first and second latches having respective outputs, the first latch having an input coupled to an output of the first inverting stage and the second latch having an input coupled to an output of the second inverting stage, wherein the first and second latches are operable to latch a present state of the input signal;
• and
• first and second logic gates, the first logic gate coupled between the output of the first inverting stage and the input of the first latch, and the second logic gate coupled between the output of the second inverting stage and the input of the second latch;
• wherein the system is operable to cease conducting current after the present state of the input signal has been latched;
• wherein the first and second logic gates are configured to prevent current flow to the first and/or second latches in case the output of the first inverting stage and/or the output of the second inverting stage is/are floating.

A system for detecting an input voltage level, the system comprising:

• an input node configured to receive an input signal;
• first and second diode-connected transistors having respective drain terminals coupled to the input node, wherein the first and second diode-connected transistors are operable to set an intermediate voltage at the input node if the input signal is open;
• first and second inverting stages having respective inputs coupled to the input node, wherein the first and second inverting stages are operable to distinguish whether the input signal is low, high, and/or open;
• and
• first and second latches having respective outputs, the first latch having an input coupled to an output of the first inverting stage and the second latch having an input coupled to an output of the second inverting stage, wherein the first and second latches are operable to latch a present state of the input signal;
• wherein the system is operable to cease conducting current after the present state of the input signal has been latched;
• wherein the first inverting stage is configured to provide a high voltage trip point and the second inverting stage is configured to provide a low voltage trip point;
• wherein when the input signal is lower than the low voltage trip point, the latched present state of the input signal is indicated by the output of the first latch being high and the output of the second latch being high;
• wherein when the input signal is open or is higher than or equal the low voltage trip point and is lower than or equal to the high voltage trip point, the latched present state of the input signal is indicated by the output of the first latch being low and the output of the second latch being high;
• and
• wherein when the input signal is higher than the high voltage trip point, the latched present state of the input signal is indicated by the output of the first latch being high and the output of the second latch being low.

A system for detecting an input voltage level, the system comprising:

• an input node configured to receive an input signal;
• first and second diode-connected transistors having respective drain terminals coupled to the input node, wherein the first and second diode-connected transistors are operable to set an intermediate voltage at the input node if the input signal is open;
• first and second inverting stages having respective inputs coupled to the input node, wherein the first and second inverting stages are operable to distinguish whether the input signal is low, high, and/or open;
• first and second latches having respective outputs, the first latch having an input coupled to an output of the first inverting stage and the second latch having an input coupled to an output of the second inverting stage, wherein the first and second latches are operable to latch a present state of the input signal;
• a third transistor having a channel terminal coupled to the input node, wherein the third transistor is configured to reduce quiescent current after the present state of the input signal has been latched;
• wherein the third transistor has a control terminal configured to receive a first control signal, wherein the first control signal is derived from the respective outputs of the first and second latches, wherein the control signal is operable to turn on the third transistor after the present state of the input signal has been latched;
• and
• wherein the system is operable to cease conducting current after the present state of the input signal has been latched.