Semiconductor integrated circuit device

A semiconductor integrated circuit device having a pulse generator outputting a pulse signal according to an input signal, and a latch circuit outputting an output signal according to the pulse signal, wherein:

• the pulse generator comprising:
• a first charge/discharge path sharing part of a path with the latch circuit;
• a first charge unit, connected to the first charge/discharge path, and configured to pre-charge a first node acting as an output end of the pulse signal;
• a first switching unit, disposed between the first node and a second node on the shared path, and configured to control according to the input signal, conduction and non-conduction of the first charge/discharge path;
• and
• a second switching unit, disposed between the second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to permit the first node to discharge, and
• the latch circuit comprising:
• a second charge/discharge path having the shared path;
• a second charge unit, connected to the second charge/discharge path, and configured to charge according to the pulse signal, a third node acting as an output end of the output signal;
• and
• a third switching unit, disposed between the third node and the second node, and configured to control according to the input signal, conduction and non-conduction of the second charge/discharge path.

A semiconductor integrated circuit device having a pulse generator outputting according to a differential input signal, a set pulse signal and a reset pulse signal, and a latch circuit outputting according to the set pulse signal and the reset pulse signal, a differential output signal, the pulse generator comprising:

• a first charge/discharge path and a second charge/discharge path sharing part of a path;
• a charge unit, connected to the first charge/discharge path and the second charge/discharge path, and configured to pre-charge first nodes acting as an output end of each of the set pulse signal and the reset pulse signal;
• two first switching units, disposed between the first nodes and a second node on the shared path, and configured to control according to the input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path, respectively;
• and
• a second switching unit, disposed between the second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge;
• wherein transistors disposed in the first switching unit and the second switching unit have lower threshold voltage Vth than that of the other transistors.