Techniques for debugging hard intellectual property blocks
AssigneeAltera Corporation
InventorsDarren van Wageningen, Boon Jin Ang
Life of this patent
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Abstract
Techniques are provided to hardware debug a programmable logic integrated circuit that includes a hardware intellectual property block (HIP). The HIP includes a logic circuit and state machine(s). The state machine outputs state machine information depending on selected signals within the logic circuit. The HIP block can also output data from a number of internal registers/flip-flops. Optional data registering logic can capture the state machine information and output it to a data bus.
Claims19
A programmable logic integrated circuit comprising a hard intellectual property block, the hard intellectual property block comprising:
- a first logic circuit configured to receive data from an external device;
- a second logic circuit configured to transmit data to the external device;
- a first state machine configured to output first state machine information depending on selected signals within the first logic circuit;
- a second state machine configured to output second state machine information depending on selected signals within the second logic circuit;
- first data registering logic configured to capture the first state machine information, the first data registering logic coupled to at least one data bus, and
- second data registering logic configured to capture the second state machine information, the second data registering logic coupled to the at least one data bus,
- wherein the at least one data bus couples with an interface of the programmable logic integrated circuit, and wherein the at least one data bus comprises:
- a first data bus dedicated to output first state machine information;
- and
- a second data bus dedicated to output second state machine information.
A method for locating a hardware design error or user mis-configuration in a hard intellectual property block of a programmable logic integrated circuit, the method comprising:
- receiving data from an external device by the hard intellectual property block;
- transmitting data to the external device by the hard intellectual property block;
- generating receive state machine information depending on a first set of selected signals within the hard intellectual property block;
- generating transmit state machine information depending on a second set of selected signals within the hard intellectual property block;
- capturing the receive and transmit state machine information;
- outputting the receive and transmit state machine information to a data bus;
- and
- determining a sequence of state transitions from the receive and transmit state machine information;
- and
- comparing the sequence of state transitions to a reference sequence of state transitions,
- wherein the data bus is accessible at an interface of the programmable logic integrated circuit, and
- wherein a software simulation generates the reference sequence.
A method for locating a hardware design error or user mis-configuration in a hard intellectual property block of a programmable logic integrated circuit, the method comprising:
- receiving data from an external device by the hard intellectual property block;
- transmitting data to the external device by the hard intellectual property block;
- generating receive state machine information depending on a first set of selected signals within the hard intellectual property block;
- generating transmit state machine information depending on a second set of selected signals within the hard intellectual property block;
- capturing the receive and transmit state machine information;
- outputting the receive and transmit state machine information to a data bus;
- and
- determining a sequence of state transitions from the receive and transmit state machine information;
- comparing the sequence of state transitions to a reference sequence of state transitions;
- and
- alerting a user upon the occurrence of a difference in the sequence of state transitions and the reference sequence,
- wherein the data bus is accessible at an interface of the programmable logic integrated circuit.
Dependencies are inferred from the claim text.