Variable impedance sense architecture and method
AssigneeCypress Semiconductor Corporation
InventorsKalyana C. Vullaganti, Jeffery Scott Hunt
Life of this patent
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Abstract
A variable impedance sense (VIS) circuit (600) can detect and store an input offset value inherent in a sensing loop (620 and/or 622). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.
Claims19
A variable impedance sense circuit, comprising:
- a comparator having at least one input coupled to a first array of switchable impedance elements;
- an offset value circuit that provides an offset value corresponding to an input offset voltage from at least one input of the comparator;
- and
- a counter circuit that receives impedance calibration bit values from the comparator, the counter circuit outputting an initial set of calibration bit values when the offset value has one predetermined value, and outputting modified calibration bit values, by modifying the initial set of calibration bit values, when the offset value has another predetermined value.
A method of sensing an impedance value for I/O matching that can compensate for an input offset voltage, comprising the steps of:
- detecting the polarity of an input offset voltage from at least one input of a comparator by switching a reference voltage to both inputs of the comparator and storing an output value from the comparator;
- generating a digital value corresponding to a reference impedance with an analog-to-digital conversion using the comparator;
- and adjusting the digital value according to the polarity of the input offset voltage.
A variable impedance sensing architecture, comprising:
- an offset register for storing an offset value corresponding to at least an input offset voltage at an input of a comparator;
- a control block coupled to the offset register that outputs an offset indication according to the offset value;
- and
- a counter circuit that adjusts a binary value generated by successive approximations in response to a predetermined offset indication value.
Dependencies are inferred from the claim text.