Output buffer with switchable output impedance

An output buffer, comprising:

• a first drive circuit having an output adapted to drive a signal line terminated with a termination resistor;
• and
• a means for switching the output impedance of said first drive circuit between a first, relatively low output impedance when said output buffer is operated in a first mode and a second output impedance which is greater than said first output impedance when said output buffer is operated in a second mode, so as to reduce the power dissipation in said termination resistor when said output buffer is operated in said second mode;
• wherein said output buffer is contained within an address register which contains a plurality of said output buffers, said buffers arranged to provide respective output signals which drive respective signal lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on a Dual-Inline Memory Module (DIMM), and
• wherein said RAM chips include respective receivers for each of said address or control inputs, each of said receivers coupled to a respective one of said signal lines and having an associated power consumption which is greatest when the voltage on said signal line is within a known range, said means for switching the output impedance of said drive circuit arranged to ensure that the voltage on said signal line is outside of said known range when said output buffer is operated in said second mode.

An output buffer, comprising:

• a first drive circuit having an output adapted to drive a signal line terminated with a termination resistor;
• and
• a means for switching the output impedance of said first drive circuit between a first, relatively low output impedance when said output buffer is operated in a first mode and a second output impedance which is greater than said first output impedance when said output buffer is operated in a second mode, so as to reduce the power dissipation in said termination resistor when said output buffer is operated in said second mode;
• wherein said means for switching the output impedance of said first drive circuit comprises:
• a first switch/resistance pair, comprising:
• a resistance which is connected in series with said drive circuit output;
• and
• a switch connected across said resistance which is opened and closed in response to a control signal, said switch closed in said first mode such that a relatively low output impedance is presented to said signal line, and said switch opened in said second mode such that an output impedance approximately equal to said resistance is presented to said signal line.

A memory system, comprising:

• a plurality of signal lines which route signals from respective output buffers to the address or control inputs of a plurality of random-access memory (RAM) chips residing on a Dual-Inline Memory Module (DIMM), said RAM chips including respective receivers for each of said address or control inputs, each of said receivers coupled to a respective one of said signal lines and having an associated power consumption which is greatest when the voltage on said signal line is within a known range;
• and
• a plurality of termination resistors connected between a fixed voltage and respective ones of said signal lines to terminate said signal lines;
• each of said output buffers comprising:
• a drive circuit having an output connected to drive a respective one of said terminated signal lines;
• and
• a means for switching the output impedance of said drive circuit between a first, relatively low output impedance when said output buffer is operated in a first mode and a second output impedance which is greater than said first output impedance when said output buffer is operated in a second mode so as to reduce the power dissipation in said termination resistor and to ensure that the voltage on said signal line is outside of said known range when said output buffer is operated in said second mode.