Circuitry and method to measure a duty cycle of a clock signal
AssigneeIntel Corporation
InventorsMukul Kelkar, Andrew M. Volk, Rajesh Kanakath, Vui Y. Liew
Life of this patent
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Abstract
In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.
Claims20
A chip comprising:
- clock generation circuitry to create a clock signal;
- reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal;
- a counter to change a count value in response to changes in the reference signal;
- and
- count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester.
A chip comprising:
- clock generation circuitry to create a clock signal;
- reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal;
- a counter to change a count value in response to changes in the reference signal;
- count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal;
- a target storage circuit to store target values related to high and low acceptable duty cycles, and comparison circuitry to compare values in the count storage circuitry with the target values.
A system comprising:
- a tester;
- a chip coupled to the tester, the chip including:
- clock generation circuitry to create a clock signal;
- reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal;
- a counter to change a count value in response to changes in the reference signal;
- and
- count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to the tester.
Dependencies are inferred from the claim text.