US 7,479,705 B2Granted

Semiconductor device

AssigneeRenesas Technology Corp.

InventorNoriyuki Takahashi

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Abstract

A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Claims9

Dependent claims

A semiconductor device comprising:

a base material having a main surface and a rear surface opposing to the main surface;
a plurality of bonding electrodes formed along a peripheral portion of the main surface of the base material;
a plurality of wirings respectively connected with each of the plurality of bonding electrodes and formed only inside of the plurality of bonding electrodes such that the bonding electrodes are located between the plurality of wirings and the peripheral portion of the main surface of the base material;
a first dummy pattern formed at a central portion of the main surface of the base material;
a first insulating film formed over the main surface of the base material such that both the plurality of wirings and the first dummy pattern are substantially covered with the first insulating film;
a plurality of bump lands formed on the rear surface of the base material;
a second dummy pattern formed at a central portion of the rear surface of the base material;
a second insulating film formed on the rear surface of the base material such that each of the plurality of bump lands is exposed from the second insulating film and the second dummy pattern is covered with the second insulating film;
a semiconductor chip mounted over the first insulating film by way of a paste material, the semiconductor chip having a main surface and a plurality of pads formed on the main surface, wherein the first insulating film separates the semiconductor chip from the plurality of wirings;
a plurality of wires electrically connecting the plurality of pads of the semiconductor chip with the plurality of bonding electrodes formed on the main surface of the base material, respectively;
a sealing body sealing the semiconductor chip, the plurality of wires and the main surface of the base material;
and
a plurality of external terminals formed on the plurality of bump lands, respectively;
wherein the first insulating film is not formed between each of the plurality of bonding electrodes and the closest peripheral edges of the peripheral portion of the base material;
wherein a concaved portion is formed at the first insulating film located between each of the plurality of bonding electrodes and the semiconductor chip;
and
wherein the peripheral portion of the main surface of the base material, which is not covered with the first insulating film, is contacted with the sealing body.

14 more elements

A semiconductor device comprising:

a base material having a main surface and a rear surface opposing to the main surface;
a plurality of bonding electrodes formed along a peripheral portion of the main surface of the base material;
a plurality of wirings respectively connected with each of the plurality of bonding electrodes and formed only inside of the plurality of bonding electrodes such that the bonding electrodes are located between the plurality of wirings and the peripheral portion of the main surface of the base material;
a first dummy pattern formed at a central portion of the main surface of the base material;
a first insulating film formed over the main surface of the base material such that both the plurality of wirings and the first dummy pattern are substantially covered with the first insulating film;
a plurality of bump lands formed on the rear surface of the base material;
a second dummy pattern formed at a central portion of the rear surface of the base material;
a second insulating film formed on the rear surface of the base material such that each of the plurality of bump lands is exposed from the second insulating film and the second dummy pattern is covered with the second insulating film;
a semiconductor chip mounted over the first insulating film by way of a paste material, the semiconductor chip having a main surface and a plurality of pads formed on the main surface, wherein the first insulating film separates the semiconductor chip from the plurality of wirings;
a plurality of wires electrically connecting the plurality of pads of the semiconductor chip with the plurality of bonding electrodes formed on the main surface of the base material, respectively;
a sealing body sealing the semiconductor chip, the plurality of wires and the main surface of the base material;
and
a plurality of external terminals formed on the plurality of bump lands, respectively;
wherein the first insulating film is not formed between each of the plurality of bonding electrodes and the closest peripheral edges of the peripheral portion of the base material;
wherein a concaved portion is formed at the first insulating film located between each of the plurality of bonding electrodes and the semiconductor chip;
and
wherein the peripheral portion of the main surface of the base material, which is not covered with the first insulating film, is covered with the sealing body;
wherein a plurality of through holes are formed in the base material, and
wherein the plurality of bump lands are connected with the plurality of through holes, respectively;
wherein at least one of the first insulating film or the second insulating film are injected inside of opening portion of each of the plurality of through holes;
wherein the concaved portion is formed as an elongated region extending substantially parallel to a peripheral edge of the main surface of the base material at the peripheral portion thereof, and located between the plurality of bonding electrodes and an outer edge of the paste material mounting the semiconductor chip to protect the bonding electrodes from coming into contact with the paste material by providing a concaved portion for the paste material to flow into;
and
wherein the plurality of wirings are connected with the plurality of through holes, respectively.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/927,106Filed 27 Aug 2004
Priority: JP 2003-30385828 Aug 2003
Published: US 2005/0046023 A13 Mar 2005
Granted: 20 Jan 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H10W 72/5445
Dispositions of bond wires: being orthogonal to a side surface of the chip, e.g. parallel arrangements
H10W 72/5522
Comprising metals or metalloids, e.g. silver: comprising gold [Au]
H10W 74/00
Encapsulations