Method and apparatus that provides differential connections with improved ESD protection and routing
AssigneeCalifornia Micro Devices Corporation
InventorsJeffrey C Dunnihoo, Chadwick N. Marak, Michael S. Evans
Life of this patent
Estimating the term…
Abstract
The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.
Claims22
An integrated circuit electrostatic discharge protection device that reduces parasitics on a printed circuit board to which the device is mounted, the device comprising:
- an integrated circuit chip that includes a plurality of ESD elements;
- a plurality of pads disposed on a periphery of the integrated circuit, the plurality of pads including:
- a first set of pads disposed on a first central peripheral region on a first side of the integrated circuit chip;
- a second set of pads disposed on a second central peripheral region on a second side of the integrated circuit chip, the second central peripheral region and the first central peripheral region being on opposite sides of the integrated circuit chip and being aligned with each other;
- a third set of pads disposed on edge peripheral regions of the integrated circuit chip;
- a leadframe package having pins that correspond to positions of the plurality of pads, including first symmetric central leadframe pins that correspond to the first set of pads, second symmetric central leadframe pins that correspond to the second set of pads, and third leadframe pins that correspond to the third set of pads;
- and
- a plurality of wires that each connect between one of the pads and one of the pins of the leadframe package, wherein
- the first and second symmetric central leadframe pins are straight and project perpendicularly from the leadframe package.
An integrated circuit electrostatic discharge protection device that reduces parasitics on a printed circuit board to which the device is mounted, the device comprising:
- an integrated circuit chip that includes a plurality of ESD elements;
- a plurality of pads disposed on a periphery of the integrated circuit, the plurality of pads including:
- a first set of pads disposed on a first central peripheral region on a first side of the integrated circuit chip;
- a second set of pads disposed on a second central peripheral region on a second side of the integrated circuit chip, the second central peripheral region and the first central peripheral region being on opposite sides of the integrated circuit chip and being aligned with each other;
- a third set of pads disposed on edge peripheral regions of the integrated circuit chip;
- a leadframe package having pins that correspond to positions of the plurality of pads, including first symmetric central leadframe pins that correspond to the first set of pads, second symmetric central leadframe pins that correspond to the second set of pads, and third leadframe pins that correspond to the third set of pads;
- and
- a plurality of wires that each connect between one of the pads and one of the pins of the leadframe package wherein,
- the printed circuit board includes a plurality of straight through parallel routing lines and, interposed between some of the straight through parallel routing lines is a ground line, each ground line being parallel to the straight parallel ground lines.
An integrated circuit electrostatic discharge protection device that reduces parasitics on a printed circuit board to which the device is mounted, the device comprising:
- an integrated circuit chip that includes a plurality of ESD elements;
- a plurality of pads disposed on a periphery of the integrated circuit, the plurality of pads including:
- a first set of pads disposed on a first central peripheral region on a first side of the integrated circuit chip;
- a second set of pads disposed on a second central peripheral region on a second side of the integrated circuit chip, the second central peripheral region and the first central peripheral region being on opposite sides of the integrated circuit chip and being aligned with each other;
- a third set of pads disposed on edge peripheral regions of the integrated circuit chip;
- a leadframe package having pins that correspond to positions of the plurality of pads, including first symmetric central leadframe pins that correspond to the first set of pads, second symmetric central leadframe pins that correspond to the second set of pads, and third leadframe pins that correspond to the third set of pads;
- and
- a plurality of wires that each connect between one of the pads and one of the pins of the leadframe package, wherein
- other circuits having signals that are not sensitive to parasitics are connected to the third set of pads.
A circuit module comprising:
- a printed circuit board that includes a plurality of straight through parallel routing lines;
- a connector mounted to the printed circuit board, the connector having connection pins that are associated with a plurality of high-speed lines;
- a processor mounted to the printed circuit board, the processor having inputs for the high speed lines;
- a plurality of parallel printed circuit board trace connections that electrically connect each of the high speed lines on the connection pins to the respective processor inputs;
- and
- an ESD package having a plurality of central pins on opposite sides of the ESD package, wherein the plurality of straight through parallel routing lines connect opposite central pins, and a plurality of ESD elements, wherein the high speed lines are each connected to one of the central pins on the ESD package that is also electrically connected to one of the parallel printed circuit board trace connections.
Dependencies are inferred from the claim text.