Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

A non-volatile memory system formed on a semiconductor substrate, comprising:

• (a) an array of memory charge storage transistors, comprising:
• a plurality of eight or more conductive word lines with lengths extending across the substrate in a first direction and adjacent each other in a second direction with a layer of dielectric therebetween but without source and drain regions therebetween, the first and second directions being orthogonal with each other, and
• regions of dielectric charge trapping material sandwiched between the conductive word lines and a surface of the substrate in a manner to provide a plurality of eight or more series connected storage transistors in individual columns extending in the second direction between terminations thereof, and
• (b) circuits peripheral to the array, comprising:
• a programming circuit that includes a source of voltages connectable to the array to cause charge to be transferred into addressed regions of dielectric charge trapping material by Fowler-Nordheim tunneling, and
• a reading circuit including a source of voltages and sensing circuits connectable to terminations of the columns of the array that determine a parameter related to a level of charge stored in dielectric regions along an addressed word line and within addressed columns of storage transistors.

A non-volatile memory system formed on a semiconductor substrate, comprising:

• (a) an array of memory charge storage transistors, comprising:
• a plurality of eight or more conductive word lines with lengths extending across the substrate in a first direction and neighboring each other in a second direction, the first and second directions being orthogonal with each other, and
• regions of dielectric charge trapping material sandwiched between the conductive word lines and a surface of the substrate in a manner to provide a plurality of eight or more series connected storage transistors in individual columns extending in the second direction between terminations thereof,
• (b) circuits peripheral to the array, comprising:
• a programming circuit that includes a source of voltages connectable to the array in a manner that causes charge to be transferred into addressed regions of dielectric charge trapping material, wherein the programming circuit is characterized by causing charge to be transferred into addressed individual regions of dielectric charge trapping material to program them into one of more than two threshold levels corresponding to data being programmed, and
• a reading circuit that includes a source of voltages connectable to the array that determine a parameter related to a level of charge stored in an addressed one of said dielectric regions within the at least one addressed column, wherein the reading circuit is characterized by generating a parameter related to the programmed more than two threshold levels of the addressed one of said dielectric regions, wherein more than one bit of data are stored in the individual regions of dielectric charge trapping material.