US 7,479,673 B2 · Semiconductor integrated circuits with stacked node contact structures

Abstract

Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Claims37

Dependent claims

An integrated circuit comprising:

a first transistor having first and second impurity regions formed at a semiconductor substrate;
a first interlayer insulating layer on the first transistor;
a second transistor having first and second impurity regions on the first interlayer insulating layer opposite the first transistor;
a second interlayer insulating layer on the second transistor opposite the first interlayer insulating layer;
a third transistor having first and second impurity regions on the second interlayer insulating layer opposite the second transistor;
a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer;
and
a node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another.

5 more elements

A static random access memory (SRAM) cell comprising:

a first bulk transistor having a first impurity region formed at least partially in a semiconductor substrate;
a second bulk transistor having a first impurity region formed at least partially in the semiconductor substrate;
a first interlayer insulating layer on the first and second bulk transistors;
a first lower thin film transistor having a first impurity region on the first interlayer insulating layer;
a second lower thin film transistor having a first impurity region on the first interlayer insulating layer;
a second interlayer insulating layer on the first and second lower thin film transistors;
a first upper thin film transistor having a first impurity region on the second interlayer insulating layer;
a second upper thin film transistor having a first impurity region on the second interlayer insulating layer;
a third interlayer insulating layer on the first and second upper thin film transistors;
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first bulk transistor, the first impurity region of the first lower thin film transistor and the first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the second bulk transistor, the first impurity region of the second lower thin film transistor and the first impurity region of the second upper thin film transistor to one another;
a first lower node semiconductor plug between the first impurity region of the first lower thin film transistor and the first impurity region of the first bulk transistor;
a first upper node semiconductor plug between the first impurity region of the first upper thin film transistor and the first impurity region of the first lower thin film transistor;
a second lower node semiconductor plug between the first impurity region of the second lower thin film transistor and the first impurity region of the second bulk transistor;
and
a second upper node semiconductor plug between the first impurity region of the second upper thin film transistor and the first impurity region of the second lower thin film transistor,
wherein the first node plug is electrically connected to the first lower node semiconductor plug and the first upper node semiconductor plug, and wherein the second node plug is electrically connected to the second lower node semiconductor plug and the second upper node semiconductor plug,
wherein the first and second upper node semiconductor plugs and the first and second lower node semiconductor plugs each comprise single crystalline semiconductor plugs, and wherein the first and second node plugs each comprise metal plugs.

15 more elements

A static random access memory (SRAM) cell comprising:

an isolation layer in a semiconductor substrate that defines first and second active regions;
a first bulk transistor and a second bulk transistor at least partially in the first and second active regions, respectively;
a first interlayer insulating layer on the first and second bulk transistors;
a first single crystalline lower body pattern and a second single crystalline lower body pattern on the first interlayer insulating layer;
a first lower thin film transistor and a second lower thin film transistor at the first and second lower body patterns, respectively;
a second interlayer insulating layer on the first and second lower thin film transistors;
a first single crystalline upper body pattern and a second single crystalline upper body pattern on the second interlayer insulating layer;
a first upper thin film transistor and a second upper thin film transistor at the first and second upper body patterns, respectively;
a third interlayer insulating layer on the first and second upper thin film transistors;
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another;
a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region;
a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region and
a ground line that is electrically connected to the first and second around active regions,
wherein the ground line crosses over the first and second active regions,
wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively,
wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and
wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor.

15 more elements

A static random access memory (SRAM) cell comprising:

an isolation layer in a semiconductor substrate that defines first and second active regions;
a first bulk transistor and a second bulk transistor at least partially in the first and second active regions, respectively;
a first interlayer insulating layer on the first and second bulk transistors;
a first single crystalline lower body pattern and a second single crystalline lower body pattern on the first interlayer insulating layer;
a first lower thin film transistor and a second lower thin film transistor at the first and second lower body patterns. respectively;
a second interlayer insulating layer on the first and second lower thin film transistors;
a first single crystalline upper body pattern and a second single crystalline upper body pattern on the second interlayer insulating layer;
a first upper thin film transistor and a second upper thin film transistor at the first and second upper body patterns. respectively;
a third interlayer insulating layer on the first and second upper thin film transistors;
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another;
a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region,
a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region,
wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively,
wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and
wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor, and
wherein the first and second lower thin film transistors are first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors are first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor, and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor,
wherein the first lower body pattern overlaps the first active region, and wherein the second lower body pattern overlaps the second active region. and wherein the first upper body pattern overlaps the first lower body pattern, and wherein the second upper body pattern overlaps the second lower body pattern.
wherein the first lower body pattern further includes an extension that overlaps a portion of the first ground active region, and wherein the second lower body pattern further includes an extension that overlaps a portion of the second ground active region.

16 more elements

A static random access memory (SRAM) cell comprising:

an isolation layer in a semiconductor substrate that defines first and second active regions;
a first bulk transistor and a second bulk transistor at least partially in the first and second active regions, respectively;
a first interlayer insulating layer on the first and second bulk transistors;
a first single crystalline lower body pattern and a second single crystalline lower body pattern on the first interlayer insulating layer;
a first lower thin film transistor and a second lower thin film transistor at the first and second lower body patterns, respectively;
a second interlayer insulating layer on the first and second lower thin film transistors;
a first single crystalline upper body pattern and a second single crystalline upper body pattern on the second interlayer insulating layer;
a first upper thin film transistor and a second upper thin film transistor at the first and second upper body patterns, respectively;
a third interlayer insulating layer on the first and second upper thin film transistors;
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another;
a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region;
a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region,
a first bit line and a second bit line that is parallel to the first bit line,
wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively,
wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and
wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor, and
wherein the first and second lower thin film transistors are first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors are first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor, and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor,
wherein the first bit line is electrically connected to a drain region of the first transfer transistor;
wherein the second bit line is electrically connected to a drain region of the second transfer transistor;
and
wherein the first and second bit lines cross over the first and second ground active regions.

19 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuits with stacked node contact structures

Life of this patent

Semiconductor integrated circuits with stacked node contact structures

Life of this patent

Abstract

Claims37