US 7,479,668 B2 · Source/drain extension implant process for use with short time anneals

Abstract

The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

Claims7

Dependent claims

A metal oxide semiconductor (MOS) device, comprising:

a substrate having a top surface;
a gate structure on said top surface;
and
a source/drain extension in said silicon substrate, wherein a portion of said source/drain extension is under said gate and said source/drain extension has a border having a maximum depth of about 25 nanometers or less from said top surface, wherein said border is defined as the location where there is an abruptness of less than about 30 Angstroms/decade.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

11/370,339Filed 8 Mar 2006 · division

Priority

10 May 2004

Published

US 2006/0177985 A110 Aug 2006

Granted

20 Jan 2009

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10P 30/222
Into semiconductor materials, e.g. for doping: characterised by the angle between the ion beam and the crystal planes or the main crystal surface
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

Application10/842,308Parent of this division · filed 10 May 2004

US 2006/0177985 A1Pre-grant publication · published 10 Aug 2006

US 7,297,605 B2Parent of this division · filed 20 Nov 2007

US 2005/0250288 A1Published application

US 7,479,668 B2This patent

From the US filing history. Foreign family members aren’t listed.

Source/drain extension implant process for use with short time anneals

Life of this patent

Source/drain extension implant process for use with short time anneals

Life of this patent

Abstract

Claims7