Post passivation interconnection schemes on top of the IC chips
AssigneeMegica Corporation
InventorsMou-Shiung Lin, Jin-Yuan Lee
Life of this patent
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Claims20
A method for fabricating a chip, comprising:
- providing a silicon substrate, an ESD circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said ESD circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said first internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process;
- and
- forming a third interconnecting structure over said silicon substrate, wherein said ESD circuit is connected to said first internal circuit though, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
A method for fabricating a chip, comprising:
- providing a silicon substrate, an ESD circuit in or on said silicon substrate, and a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said ESD circuit, and wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process;
- and
- forming a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said ESD circuit through said first interconnecting structure, and wherein said forming said second interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
Dependencies are inferred from the claim text.