Semiconductor device and method of manufacturing the same

A method of manufacturing at least first and second regions of a semiconductor device, the method comprising:

• forming a first preliminary gate structure and a second preliminary gate structure including uppermost polysilicon layers, respectively, on first and second regions of a substrate, respectively;
• forming first and second impurity regions in the substrate at each of both sides of the first preliminary gate structure and the second preliminary gate structure;
• forming spacers against sidewalls of the first preliminary gate structure and the second preliminary gate structure;
• forming a first silicidation-controlling layer pattern on the substrate in the first region and a second silicidation-controlling layer pattern on the substrate and on the second preliminary gate structure in the second region, the first silicidation-controlling layer pattern selectively exposing the first preliminary gate structure and having a thickness sufficiently thin so that a subsequent silicidation reaction on the substrate could occur;
• forming a metal layer on the first preliminary gate structure, the silicidation-controlling layer pattern, the spacers and the silicidation-blocking layer pattern;
• and
• reacting the metal layer with the first preliminary gate structure and the substrate underneath the first solicidation-controlling layer pattern to form a first gate structure and a second silicide layer pattern on the first impurity region, respectively, the first gate structure including an uppermost first metal silicide layer pattern having a first thickness, and the second silicide layer pattern having a second thickness thinner than the first thickness.

A method of manufacturing a semiconductor device, comprising:

• forming a first preliminary gate structure and a second preliminary gate structure including uppermost polysilicon layers, respectively, on first and second regions of a substrate, respectively,
• forming first and second impurity regions in the substrate at each of both sides of the first preliminary gate structure and the second preliminary gate structure,
• forming spacers against sidewalls of the first preliminary gate structure and the second preliminary gate structure,
• forming a silicidation-blocking layer on the first preliminary gate structure, the second gate structure, the spacers and the substrate,
• forming a photoresist structure masking a portion of the substrate between the first preliminary gate structures and another portion of the substrate corresponding substantially to the entire second region,
• partially etching the silicidation-blocking layer using the photoresist structure as an etching mask to form a silicidation-blocking layer pattern selectively exposing the first preliminary gate structure,
• forming a metal layer on the first preliminary gate structure and the silicidation-blocking layer pattern, and
• reacting the metal layer with the first preliminary gate structure to form a first gate structure including a first metal silicide layer pattern in the first region.

A method of manufacturing a semiconductor device, comprising:

• forming a first preliminary gate structure and a second preliminary gate structure including uppermost polysilicon layers, respectively, on first and second regions of a substrate, respectively,
• forming first and second impurity regions in the substrate at each of both sides of the first preliminary gate structure and the second gate structure,
• forming spacers on sidewalls of the first preliminary gate structure and the second preliminary gate structure,
• forming a silicidation-blocking layer pattern on the second region,
• covering the first preliminary gate structure and the second preliminary gate structure with a fluidic oxide layer,
• etching the fluidic oxide layer to form a fluidic oxide layer pattern on a portion of the substrate located between the first preliminary gate structures,
• forming a metal layer on the first preliminary gate structure and the silicidation-blocking layer pattern, and
• reacting the metal layer with the first preliminary gate structure to form a first gate structure including a first metal silicide layer pattern in the first region.