Split game memory cell method
AssigneeFreescale Semiconductor, Inc.
InventorsRajesh Rao, Ramachandran Muralidhar, Leo Mathew
Life of this patent
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Abstract
A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.
Claims20
A method for forming a split-gate memory cell using a semiconductor substrate, comprising:
- forming a storage layer over the substrate;
- forming a first conductive layer over the storage layer;
- reducing a thickness of a portion of the conductive layer to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer;
- forming a first sidewall spacer adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer;
- replacing the pillar with a select gate;
- and
- selectively removing the area of reduced thickness to leave the first and second portions as control gates.
A method for forming a split-gate memory cell using a semiconductor substrate, comprising:
- forming a storage layer over the substrate;
- forming a first polysilicon layer having a thickness over the storage layer;
- forming a nitride layer over the polysilicon layer;
- forming a masking layer having a pattern over the nitride layer;
- etching through the nitride layer according to the pattern;
- etching a portion of the polysilicon layer according to the pattern to leave a pillar of polysilicon under the masking layer and an area of reduced thickness of polysilicon surrounding the pillar;
- forming a first nitride sidewall spacer around the pillar to cover a portion of the area of reduced thickness and leaving an exposed portion of the area of reduced thickness;
- growing polysilicon over the exposed portion of the area of reduced thickness to form an area of enhanced thickness of polysilicon;
- oxidizing a top portion of the area of enhanced thickness of polysilicon to form a top oxide layer;
- removing the pillar to form an opening;
- replacing the first nitride sidewall spacer with a second nitride sidewall spacer;
- depositing a second polysilicon layer in the opening, over the second nitride sidewall spacer, and over the top oxide layer;
- etching back the second polysilicon layer to leave a polysilicon portion in the opening;
- removing the top oxide layer;
- while using the second nitride sidewall spacer as a mask, removing the area of enhanced thickness of polysilicon and the charge storage layer to leave a polysilicon remnant under the second sidewall spacer;
- and
- forming source/drains in the substrate spaced from the polysilicon portion in the opening.
A method for forming a split-gate memory cell using a semiconductor substrate, comprising:
- forming a storage layer over the substrate;
- forming a first conductive layer over the storage layer;
- reducing a thickness of a portion of the conductive layer to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer;
- forming a first sidewall spacer adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer;
- forming an insulating layer over the area of reduced thickness;
- while using the insulating layer as a mask, replacing the pillar with a select gate;
- removing the insulating layer;
- and
- selectively removing the area of reduced thickness to leave the first and second portions as control gates.
Dependencies are inferred from the claim text.