Thin film transistor array panel and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung-Min Park, Jin-Goo Jung, Chun-Gi You
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Abstract
A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist.
Claims11
A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate;
- forming a first passivation layer on the drain and the source electrodes;
- forming a transparent conductive layer on the first passivation layer;
- etching the transparent conductive layer using a photoresist as an etch mask to expose a portion of the first passivation layer and to form a pixel electrode connected the drain electrode;
- ashing the first passivation layer and the photoresist, wherein the ashing the first passivation layer forms a step on the passivation layer, and wherein the step does not overlap the pixel electrode;
- and
- removing the photoresist.
A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a semiconductor including extrinsic regions and intrinsic regions;
- forming a gate insulating layer covering the semiconductor;
- forming a gate line overlapping the intrinsic regions of the semiconductor;
- forming an interlayer insulating layer covering the gate line and the gate insulating layer;
- forming a data line and a drain electrode respectively connected to the extrinsic regions of the semiconductor;
- forming a passivation layer covering the data line and the drain electrode;
- forming a transparent conductive layer on the passivation layer;
- etching the transparent conductive layer using a photoresist as an etch mask to expose a portion of the passivation layer and to form a pixel electrode connected the drain electrode;
- ashing the passivation layer and the photoresist, wherein the ashing the first passivation layer forms a step on the passivation layer, and wherein the step does not overlap the pixel electrode;
- and
- removing the photoresist.
Dependencies are inferred from the claim text.